From f5dd8ddc72ce829406337f22e73cac27b58aa521 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 10 Jul 2020 16:33:57 -0400 Subject: Remove overlapping inputForm=LowForm tests Remove tests from LoweringCompilerSpec testing the placement of inputForm=LowForm legacy, custom transforms. This behavior is already tested in the CustomTransformSpec. Signed-off-by: Schuyler Eldridge --- .../scala/firrtlTests/LoweringCompilersSpec.scala | 37 ---------------------- 1 file changed, 37 deletions(-) (limited to 'src/test/scala/firrtlTests/LoweringCompilersSpec.scala') diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index 82750fdf..7df621d3 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -8,7 +8,6 @@ import firrtl._ import firrtl.passes import firrtl.options.Dependency import firrtl.stage.{Forms, TransformManager} -import firrtl.transforms.IdentityTransform sealed trait PatchAction { val line: Int } @@ -339,40 +338,4 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { compare(expected, tm) } - it should "schedule inputForm=LowForm after MiddleFirrtlToLowFirrtl for the LowFirrtlEmitter" in { - val expected = - new TransformManager(Forms.LowForm).flattenedTransformOrder ++ - Seq(new Transforms.LowToLow, new firrtl.LowFirrtlEmitter) - val tm = (new TransformManager(Seq(Dependency[firrtl.LowFirrtlEmitter], Dependency[Transforms.LowToLow]))) - compare(expected, tm) - } - - it should "schedule inputForm=LowForm after MinimumLowFirrtlOptimizations for the MinimalVerilogEmitter" in { - val expected = - new TransformManager(Forms.LowFormMinimumOptimized).flattenedTransformOrder ++ - Seq(new Transforms.LowToLow, new firrtl.MinimumVerilogEmitter) - val tm = (new TransformManager(Seq(Dependency[firrtl.MinimumVerilogEmitter], Dependency[Transforms.LowToLow]))) - val patches = Seq( - Add(63, Seq( - Dependency(firrtl.transforms.formal.ConvertAsserts), - Dependency[firrtl.transforms.formal.RemoveVerificationStatements], - Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) - ) - compare(expected, tm, patches) - } - - it should "schedule inputForm=LowForm after LowFirrtlOptimizations for the VerilogEmitter" in { - val expected = - new TransformManager(Forms.LowFormOptimized).flattenedTransformOrder ++ - Seq(new Transforms.LowToLow, new firrtl.VerilogEmitter) - val tm = (new TransformManager(Seq(Dependency[firrtl.VerilogEmitter], Dependency[Transforms.LowToLow]))) - val patches = Seq( - Add(70, Seq( - Dependency(firrtl.transforms.formal.ConvertAsserts), - Dependency[firrtl.transforms.formal.RemoveVerificationStatements], - Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) - ) - compare(expected, tm, patches) - } - } -- cgit v1.2.3