From 4b8a0d2af52ceeb3ff5d05082af53bac76744361 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 22 Sep 2016 19:10:40 -0700
Subject: Add Support for Parameterized ExtModules and Name Override

Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.
---
 src/test/scala/firrtlTests/ExtModuleSpec.scala | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/test/scala/firrtlTests/ExtModuleSpec.scala')

diff --git a/src/test/scala/firrtlTests/ExtModuleSpec.scala b/src/test/scala/firrtlTests/ExtModuleSpec.scala
index ba36e5f2..b7866de1 100644
--- a/src/test/scala/firrtlTests/ExtModuleSpec.scala
+++ b/src/test/scala/firrtlTests/ExtModuleSpec.scala
@@ -31,4 +31,8 @@ class SimpleExtModuleExecutionTest extends ExecutionTest("SimpleExtModuleTester"
                                                          Seq("SimpleExtModule"))
 class MultiExtModuleExecutionTest extends ExecutionTest("MultiExtModuleTester", "/blackboxes",
                                                         Seq("SimpleExtModule", "AdderExtModule"))
+class RenamedExtModuleExecutionTest extends ExecutionTest("RenamedExtModuleTester", "/blackboxes",
+                                                          Seq("SimpleExtModule"))
+class ParameterizedExtModuleExecutionTest extends ExecutionTest(
+    "ParameterizedExtModuleTester", "/blackboxes", Seq("ParameterizedExtModule"))
 
-- 
cgit v1.2.3