From 228c9a4b7432ac52178d63b8f27fe064aec71e9c Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 24 May 2019 14:37:52 -0700
Subject: Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)

Emit Verilog IntParams that fit in 32-bits as Integer literals
---
 src/test/scala/firrtlTests/ExtModuleSpec.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/test/scala/firrtlTests/ExtModuleSpec.scala')

diff --git a/src/test/scala/firrtlTests/ExtModuleSpec.scala b/src/test/scala/firrtlTests/ExtModuleSpec.scala
index 598d6e3b..96668222 100644
--- a/src/test/scala/firrtlTests/ExtModuleSpec.scala
+++ b/src/test/scala/firrtlTests/ExtModuleSpec.scala
@@ -11,3 +11,4 @@ class RenamedExtModuleExecutionTest extends ExecutionTest("RenamedExtModuleTeste
 class ParameterizedExtModuleExecutionTest extends ExecutionTest(
     "ParameterizedExtModuleTester", "/blackboxes", Seq("ParameterizedExtModule"))
 
+class LargeParamExecutionTest extends ExecutionTest("LargeParamTester", "/blackboxes", Seq("LargeParam"))
-- 
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