From b274b319d4a4014c154f06bfc174beba461d6fce Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 18 Mar 2021 23:31:51 -0700 Subject: Ensure InlineCasts does not inline complex Expressions (#2130) Previously, InlineCasts could inline complex (ie. non-cast) Expressions into other complex Expressions. Now it will only inline so long as there no more than 1 complex Expression in the current nested Expression. Co-authored-by: Albert Magyar --- src/test/scala/firrtl/testutils/FirrtlSpec.scala | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/test/scala/firrtl/testutils') diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala index 24793437..63def26a 100644 --- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala +++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala @@ -165,10 +165,14 @@ trait FirrtlRunners extends BackendCompilationUtilities { /** Compiles input Firrtl to Verilog */ def compileToVerilog(input: String, annotations: AnnotationSeq = Seq.empty): String = { + compileToVerilogCircuitState(input, annotations).getEmittedCircuit.value + } + + /** Compiles input Firrtl to Verilog */ + def compileToVerilogCircuitState(input: String, annotations: AnnotationSeq = Seq.empty): CircuitState = { val circuit = Parser.parse(input.split("\n").toIterator) val compiler = new VerilogCompiler - val res = compiler.compileAndEmit(CircuitState(circuit, HighForm, annotations), extraCheckTransforms) - res.getEmittedCircuit.value + compiler.compileAndEmit(CircuitState(circuit, HighForm, annotations), extraCheckTransforms) } /** Compile a Firrtl file -- cgit v1.2.3