From c48c691e94afe4919c20fa588a9897316c572447 Mon Sep 17 00:00:00 2001
From: Jack
Date: Tue, 23 Feb 2016 00:57:09 -0800
Subject: Add rocket regression, just runs rocket.fir through Verilog compiler
 and compares to expected Verilog. Uses ScalaTest. Should be eventually
 replaced with actual simulation of rocket-chip

---
 src/test/resources/regress | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 src/test/resources/regress

(limited to 'src/test/resources')

diff --git a/src/test/resources/regress b/src/test/resources/regress
new file mode 120000
index 00000000..3691434b
--- /dev/null
+++ b/src/test/resources/regress
@@ -0,0 +1 @@
+../../../regress
\ No newline at end of file
-- 
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