From e05ca2b2edb3b1d3fc191864ff31e2b5fc079b42 Mon Sep 17 00:00:00 2001
From: Donggyu
Date: Sat, 5 Nov 2016 21:23:14 -0700
Subject: Fix CHIRRTL bugs (#355)

* handle uninferred ports gracefully in RemoveCHIRRTL

memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL

* fix CInferTypes
---
 src/test/resources/features/EmptyChirrtlMem.fir | 5 +++++
 src/test/resources/features/NodeType.fir        | 8 ++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 src/test/resources/features/EmptyChirrtlMem.fir
 create mode 100644 src/test/resources/features/NodeType.fir

(limited to 'src/test/resources/features')

diff --git a/src/test/resources/features/EmptyChirrtlMem.fir b/src/test/resources/features/EmptyChirrtlMem.fir
new file mode 100644
index 00000000..036d3830
--- /dev/null
+++ b/src/test/resources/features/EmptyChirrtlMem.fir
@@ -0,0 +1,5 @@
+circuit Queue :
+  module Queue :
+    input clock : Clock
+    cmem ram : UInt<1>[2]
+    infer mport T_107 = ram[UInt(0)], clock
diff --git a/src/test/resources/features/NodeType.fir b/src/test/resources/features/NodeType.fir
new file mode 100644
index 00000000..fe48871b
--- /dev/null
+++ b/src/test/resources/features/NodeType.fir
@@ -0,0 +1,8 @@
+circuit NodeType :
+  module NodeType :
+    input clock : Clock
+
+    cmem rf : UInt<64>[31]
+    node rf_wdata = mux(UInt(0), UInt(0), UInt(0))
+    infer mport port = rf[UInt(0)], clock
+    port <- rf_wdata
-- 
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