From 297fbda180584cc3456145faecdc40418babeef1 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 31 Oct 2018 09:21:05 -0700
Subject: Don't include verilog header files in "FileList" for VCS/Verilator.
 (#918)

When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917---
 .../resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v   | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v

(limited to 'src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v')

diff --git a/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v b/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v
new file mode 100644
index 00000000..fcba38d5
--- /dev/null
+++ b/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v
@@ -0,0 +1,8 @@
+// See LICENSE for license details.
+module ParameterizedViaHeaderAdderExtModule(
+  input [15:0] foo,
+  output [15:0] bar
+);
+  `include "VerilogHeaderFile.vh"
+  assign bar = foo + VALUE;
+endmodule
-- 
cgit v1.2.3