From 4c3b4f4dc10c380a101df75cb561e3f79f1a6abe Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Fri, 23 Sep 2016 13:44:57 -0700
Subject: Add RawString ExtModule parameter support

While unsafe, this supports Verilog parameter types.
Tests now require Verilator 3.884+ to pass.
---
 src/test/resources/blackboxes/ParameterizedExtModule.v | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/test/resources/blackboxes/ParameterizedExtModule.v')

diff --git a/src/test/resources/blackboxes/ParameterizedExtModule.v b/src/test/resources/blackboxes/ParameterizedExtModule.v
index ee6e3ec3..ae5d94be 100644
--- a/src/test/resources/blackboxes/ParameterizedExtModule.v
+++ b/src/test/resources/blackboxes/ParameterizedExtModule.v
@@ -6,10 +6,13 @@ module ParameterizedExtModule(
   parameter VALUE = 0;
   parameter STRING = "one";
   parameter REAL = 1.0;
+  parameter type TYP = bit;
   wire [15:0] fizz;
   wire [15:0] buzz;
-  assign bar = foo + VALUE + fizz + buzz;
+  wire TYP tpe;
+  assign bar = foo + VALUE + fizz + buzz + tpe;
   assign fizz = (STRING == "two")? 2 : (STRING == "one")? 1 : 0;
   assign buzz = (REAL > 2.5E50)? 2 : (REAL < 0.0)? 1 : 0;
+  assign tpe = 2; // Will give 0 if bit, 2 for any larger width
 endmodule
 
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