From f24a733dc279e93a7d5d945042ec7472a6872aa1 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 29 May 2018 16:13:39 -0700
Subject: Fix pad (#817)

* Make VerilogEmitter properly handle pad of width <= width of arg

* Constant prop pads with pad amount <= width of arg
---
 src/main/scala/firrtl/Emitter.scala                        | 2 +-
 src/main/scala/firrtl/transforms/ConstantPropagation.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 9bb8a466..6ffa942c 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -264,7 +264,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
        case Pad =>
          val w = bitWidth(a0.tpe)
          val diff = c0 - w
-         if (w == BigInt(0)) Seq(a0)
+         if (w == BigInt(0) || diff <= 0) Seq(a0)
          else doprim.tpe match {
            // Either sign extend or zero extend.
            // If width == BigInt(1), don't extract bit
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index 60d9ac2c..5e9a7850 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -212,7 +212,7 @@ class ConstantPropagation extends Transform {
     case Pad => e.args.head match {
       case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v, IntWidth(e.consts.head max w))
       case SIntLiteral(v, IntWidth(w)) => SIntLiteral(v, IntWidth(e.consts.head max w))
-      case _ if bitWidth(e.args.head.tpe) == e.consts.head => e.args.head
+      case _ if bitWidth(e.args.head.tpe) >= e.consts.head => e.args.head
       case _ => e
     }
     case Bits => e.args.head match {
-- 
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