From ea558ad79ed0e65df73b5a01ceea690e5b0479ca Mon Sep 17 00:00:00 2001
From: Albert Chen
Date: Thu, 23 Jul 2020 09:39:41 -0700
Subject: Update negative literal emission (#1782)

* test const prop of addition of negative literals

* Emitter: handle minimum negative values correctly

* update expected verilog in AsyncResetSpec---
 src/main/scala/firrtl/Emitter.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index f9787a48..fdfda3e6 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -7,7 +7,7 @@ import java.io.Writer
 import scala.collection.mutable
 import firrtl.ir._
 import firrtl.passes._
-import firrtl.transforms.LegalizeAndReductionsTransform
+import firrtl.transforms.{FixAddingNegativeLiterals, LegalizeAndReductionsTransform}
 import firrtl.annotations._
 import firrtl.traversals.Foreachers._
 import firrtl.PrimOps._
@@ -286,6 +286,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
      case SIntLiteral(value, IntWidth(width)) =>
        val stringLiteral = value.toString(16)
        w write (stringLiteral.head match {
+         case '-' if value == FixAddingNegativeLiterals.minNegValue(width) => s"$width'sh${stringLiteral.tail}"
          case '-' => s"-$width'sh${stringLiteral.tail}"
          case _ => s"$width'sh${stringLiteral}"
        })
-- 
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