From c9aff1ca5bc701678a325fb662427f21c48ea1af Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Thu, 6 Feb 2020 06:17:40 -0800
Subject: [Behavior change] Andr of zero-width wire now returns UIntLiteral(1)

* Fixes #1344
---
 src/main/scala/firrtl/passes/ZeroWidth.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index 83fc1b6b..e01cfffc 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -114,6 +114,7 @@ object ZeroWidth extends Transform {
         case Seq(x) => x
         case seq => DoPrim(Cat, seq, consts, tpe) map onExp
       }
+    case DoPrim(Andr, Seq(x), _, _) if (bitWidth(x.tpe) == 0) => UIntLiteral(1) // nothing false
     case other => other.tpe match {
       case UIntType(IntWidth(ZERO)) => UIntLiteral(ZERO, IntWidth(BigInt(1)))
       case SIntType(IntWidth(ZERO)) => SIntLiteral(ZERO, IntWidth(BigInt(1)))
-- 
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