From 31313c4f561fe71009b9e40762e7638ded151162 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Sat, 26 Sep 2020 14:49:45 -0700
Subject: Handle case where rdata of mem RW port split to R+W ports drives
 another mem

---
 src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 1cecf543..8fb2dc88 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -110,7 +110,7 @@ class MemDelayAndReadwriteTransformer(m: DefModule) {
 
       val readStmts = (mem.readers ++ mem.readwriters).map {
         case r =>
-          def oldDriver(f: String) = netlist(we(memPortField(mem, r, f)))
+          def oldDriver(f: String) = swapMemRefs(netlist(we(memPortField(mem, r, f))))
           def newField(f:  String) = memPortField(newMem, rMap.getOrElse(r, r), f)
           val clk = oldDriver("clk")
 
@@ -139,7 +139,7 @@ class MemDelayAndReadwriteTransformer(m: DefModule) {
 
       val writeStmts = (mem.writers ++ mem.readwriters).map {
         case w =>
-          def oldDriver(f: String) = netlist(we(memPortField(mem, w, f)))
+          def oldDriver(f: String) = swapMemRefs(netlist(we(memPortField(mem, w, f))))
           def newField(f:  String) = memPortField(newMem, wMap.getOrElse(w, w), f)
           val clk = oldDriver("clk")
 
-- 
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