From a7fa5cd7e3c55c2bc828a04f60b6a4c41ea3876a Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 6 Mar 2017 16:07:20 -0800
Subject: After merge, fixed added transforms

---
 src/main/scala/firrtl/Emitter.scala | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 10d3ae85..b1c318fa 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -148,7 +148,11 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
         emitAllModules(state.circuit) map (EmittedFirrtlModuleAnnotation(_))
       case _ => Seq()
     }
-    state.copy(annotations = Some(AnnotationMap(newAnnos)))
+    val annos = newAnnos ++ (state.annotations match {
+      case None => Seq.empty
+      case Some(a) => a.annotations
+    })
+    state.copy(annotations = Some(AnnotationMap(annos)))
   }
 
   // Old style, deprecated
@@ -775,6 +779,10 @@ class VerilogEmitter extends Transform with PassBased with Emitter {
         }
       case _ => Seq()
     }
-    state.copy(annotations = Some(AnnotationMap(newAnnos)))
+    val annos = newAnnos ++ (state.annotations match {
+      case None => Seq.empty
+      case Some(a) => a.annotations
+    })
+    state.copy(annotations = Some(AnnotationMap(annos)))
   }
 }
-- 
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