From a399dc8afe1de04266bbe08108d067ca84089511 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 31 Oct 2016 17:05:08 -0700
Subject: Fixed Verilog emission of andr, orr, and xorr (#357)

Fixed Verilog emission reduce ops with efficient implementation
---
 src/main/scala/firrtl/Emitter.scala | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 5a4420c6..7b198149 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -223,12 +223,9 @@ class VerilogEmitter extends Emitter {
        case And => Seq(cast_as(a0), " & ", cast_as(a1))
        case Or => Seq(cast_as(a0), " | ", cast_as(a1))
        case Xor => Seq(cast_as(a0), " ^ ", cast_as(a1))
-       case Andr => (0 until bitWidth(doprim.tpe).toInt) map (
-         Seq(cast(a0), "[", _, "]")) reduce (_ + " & " + _)
-       case Orr => (0 until bitWidth(doprim.tpe).toInt) map (
-         Seq(cast(a0), "[", _, "]")) reduce (_ + " | " + _)
-       case Xorr => (0 until bitWidth(doprim.tpe).toInt) map (
-         Seq(cast(a0), "[", _, "]")) reduce (_ + " ^ " + _)
+       case Andr => Seq("&", cast(a0))
+       case Orr => Seq("|", cast(a0))
+       case Xorr => Seq("^", cast(a0))
        case Cat => Seq("{", cast(a0), ",", cast(a1), "}")
        // If selecting zeroth bit and single-bit wire, just emit the wire
        case Bits if c0 == 0 && c1 == 0 && bitWidth(a0.tpe) == BigInt(1) => Seq(a0)
-- 
cgit v1.2.3