From 94d425f0f48e84bbae1be9d44d64615a37d960d8 Mon Sep 17 00:00:00 2001
From: Alan L
Date: Fri, 3 Feb 2023 15:38:07 +0800
Subject: Fix invalid references generated by VerilogMemDelays (#2588)

Transformation of mem readwriters whose address contain references to
readwriters of mems declared before it would contain invalid references
to untransformed memory readwriter, as the connection is not transformed.
This commit fixes this issue.---
 src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 3778f4da..8bc17049 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -221,7 +221,18 @@ class MemDelayAndReadwriteTransformer(m: DefModule, passthroughSimpleSyncReadMem
   val transformed = m match {
     case mod: Module =>
       findMemConns(mod.body)
-      mod.copy(body = Block(transform(mod.body) +: newConns.toSeq))
+      val bodyx = transform(mod.body)
+      // Fixup any mem connections being driven by other transformed memories
+      val newConsx = newConns.map {
+        case sx if kind(sx.loc) == MemKind =>
+          val (memRef, _) = Utils.splitRef(sx.loc)
+          if (passthroughMems(WrappedExpression(memRef)))
+            sx
+          else
+            sx.mapExpr(swapMemRefs)
+        case sx => sx
+      }
+      mod.copy(body = Block(bodyx +: newConsx.toSeq))
     case mod => mod
   }
 }
-- 
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