From 89e9ab0bb0fd3f1f4a79eaf6209727684a2fa23f Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Thu, 25 Feb 2021 13:28:17 -0800
Subject: Emit space after 'if' for all Verilog conditional synchronous
 assignments (#2091)

---
 src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
index 3ecd1279..f1650ad7 100644
--- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
+++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
@@ -756,7 +756,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       val lines = noResetAlwaysBlocks.getOrElseUpdate(clk, ArrayBuffer[Seq[Any]]())
       if (weq(en, one)) lines += Seq(e, " <= ", value, ";")
       else {
-        lines += Seq("if(", en, ") begin")
+        lines += Seq("if (", en, ") begin")
         lines += Seq(tab, e, " <= ", value, ";", info)
         lines += Seq("end")
       }
-- 
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