From 726c808375fe513c70376bf05e76dd938e578bf9 Mon Sep 17 00:00:00 2001
From: Yunsup Lee
Date: Fri, 16 Sep 2016 13:02:06 -0700
Subject: fill empty module body with "begin end" (#305)

* fill empty module body with "begin end"

apparently vivado treats an empty module as a black box and triggers an error

* Changed empty module to use always @(*) begin end
---
 src/main/scala/firrtl/Emitter.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 26b1f3d9..92cb7a54 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -612,6 +612,7 @@ class VerilogEmitter extends Emitter {
         }
         emit(Seq(");"))
 
+        if (declares.isEmpty && assigns.isEmpty) emit(Seq(tab, "always @(*) begin end"))
         for (x <- declares) emit(Seq(tab, x))
         for (x <- instdeclares) emit(Seq(tab, x))
         for (x <- assigns) emit(Seq(tab, x))
-- 
cgit v1.2.3