From 6acc9b5c71a0ad2ba22a6f02654a564a1ec3bb08 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 23 Jan 2016 16:40:44 -0800
Subject: off by one error when emitting ports in verilog

---
 src/main/stanza/passes.stanza | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index ce222b6e..000419cc 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2608,7 +2608,7 @@ defn emit-verilog (m:InModule) -> Module :
       emit(["module " name(m) "("])
       if !empty?(portdefs) :
          for (x in portdefs, i in 0 to false) do : 
-            if i != length(portdefs) : emit([tab x ","])
+            if i != length(portdefs) - 1 : emit([tab x ","])
             else : emit([tab x])
       emit([");"])
 
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