From 66c3695550f60903efe90bb6839d0f75cad4d7fd Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Mon, 13 Apr 2020 14:01:35 -0700
Subject: Ensure PadWidths is run in mverilog compiler

---
 src/main/scala/firrtl/passes/PadWidths.scala | 5 +++--
 src/main/scala/firrtl/stage/Forms.scala      | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 0b318511..163b2270 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -17,8 +17,9 @@ object PadWidths extends Pass {
     ((new mutable.LinkedHashSet())
        ++ firrtl.stage.Forms.LowForm
        - Dependency(firrtl.passes.Legalize)
-       + Dependency(firrtl.passes.RemoveValidIf)
-       + Dependency[firrtl.transforms.ConstantPropagation]).toSeq
+       + Dependency(firrtl.passes.RemoveValidIf)).toSeq
+
+  override val optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation])
 
   override val dependents =
     Seq( Dependency(firrtl.passes.memlib.VerilogMemDelays),
diff --git a/src/main/scala/firrtl/stage/Forms.scala b/src/main/scala/firrtl/stage/Forms.scala
index 76587abc..1c3f4816 100644
--- a/src/main/scala/firrtl/stage/Forms.scala
+++ b/src/main/scala/firrtl/stage/Forms.scala
@@ -67,12 +67,12 @@ object Forms {
 
   val LowFormMinimumOptimized: Seq[TransformDependency] = LowForm ++
     Seq( Dependency(passes.RemoveValidIf),
+         Dependency(passes.PadWidths),
          Dependency(passes.memlib.VerilogMemDelays),
          Dependency(passes.SplitExpressions) )
 
   val LowFormOptimized: Seq[TransformDependency] = LowFormMinimumOptimized ++
     Seq( Dependency[firrtl.transforms.ConstantPropagation],
-         Dependency(passes.PadWidths),
          Dependency[firrtl.transforms.CombineCats],
          Dependency(passes.CommonSubexpressionElimination),
          Dependency[firrtl.transforms.DeadCodeElimination] )
-- 
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