From 4e77c5e14a05cedda621a4acdbc435bed23a202d Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Thu, 31 Jan 2019 17:10:50 -0800
Subject: Use apache commons for string escaping instead of reflection (#1008)

---
 src/main/scala/firrtl/ir/IR.scala | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index 19ee56ca..4f647c0c 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -58,15 +58,13 @@ trait HasInfo {
 trait IsDeclaration extends HasName with HasInfo
 
 case class StringLit(string: String) extends FirrtlNode {
+  import org.apache.commons.text.StringEscapeUtils
   /** Returns an escaped and quoted String */
   def escape: String = {
-    import scala.reflect.runtime.universe._
-    Literal(Constant(string)).toString
-  }
-  def serialize: String = {
-    val str = escape
-    str.slice(1, str.size - 1)
+    "\"" + serialize + "\""
   }
+  def serialize: String = StringEscapeUtils.escapeJava(string)
+
   /** Format the string for Verilog */
   def verilogFormat: StringLit = {
     StringLit(string.replaceAll("%x", "%h"))
@@ -81,6 +79,7 @@ case class StringLit(string: String) extends FirrtlNode {
   }
 }
 object StringLit {
+  import org.apache.commons.text.StringEscapeUtils
   /** Maps characters to ASCII for Verilog emission */
   private def toASCII(char: Char): List[Char] = char match {
     case nonASCII if !nonASCII.isValidByte => List('?')
@@ -94,8 +93,7 @@ object StringLit {
 
   /** Create a StringLit from a raw parsed String */
   def unescape(raw: String): StringLit = {
-    val str = StringContext.processEscapes(raw)
-    StringLit(str)
+    StringLit(StringEscapeUtils.unescapeJava(raw))
   }
 }
 
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