From 8265e2e67e39f2d313a74bccb6dd45d85f706f3a Mon Sep 17 00:00:00 2001
From: azidar
Date: Sun, 24 Jan 2016 16:30:50 -0800
Subject: Added muxing on passive aggregate types

---
 src/main/stanza/firrtl-ir.stanza | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'src/main/stanza/firrtl-ir.stanza')

diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index ace1e76f..6a69b9ac 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -45,7 +45,7 @@ public val NEQUAL-OP = new PrimOp
 public val EQUAL-OP = new PrimOp
 public val NEQUIV-OP = new PrimOp
 public val EQUIV-OP = new PrimOp
-public val MUX-OP = new PrimOp
+;public val MUX-OP = new PrimOp
 public val PAD-OP = new PrimOp
 public val AS-UINT-OP = new PrimOp
 public val AS-SINT-OP = new PrimOp
@@ -84,6 +84,11 @@ public defstruct SubAccess <: Expression :
    exp: Expression
    index: Expression
    type: Type with: (as-method => true)
+public defstruct Mux <: Expression :
+   cond: Expression
+   tval: Expression
+   fval: Expression
+   type: Type with: (as-method => true)
 public defstruct UIntValue <: Expression :
    value: BigInt
    width: Width
-- 
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