From 8feaa0a5ae0479b4063771202d7ad0e93d39c247 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 19 May 2015 14:16:06 -0700
Subject: Added support for non-inlined modules in verilog backend

---
 src/main/stanza/compilers.stanza | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/stanza/compilers.stanza')

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index e912d3a0..901f6100 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -52,7 +52,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       ExpandIndexedConnects()
       ExpandWhens()
       InferWidths()
-      Inline()
+      ;Inline()
       SplitExp()
       ToRealIR()
       Verilog(file(c))
-- 
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