From b05eaea3e59c64d619a544c63311d510f335f7e5 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Wed, 22 Aug 2018 16:08:00 -0400
Subject: Make ClockListAnnotation a RegisteredTransform

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 .../scala/firrtl/passes/clocklist/ClockListTransform.scala   | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src/main/scala')

diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
index 6b265239..8d70f211 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
@@ -57,9 +57,19 @@ Usage:
   }
 }
 
-class ClockListTransform extends Transform {
+class ClockListTransform extends Transform with RegisteredTransform {
   def inputForm = LowForm
   def outputForm = LowForm
+
+  def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser
+    .opt[String]("list-clocks")
+    .abbr("clks")
+    .valueName ("-c:<circuit>:-m:<module>:-o:<filename>")
+    .action( (x, c) => c ++ Seq(passes.clocklist.ClockListAnnotation.parse(x),
+                                RunFirrtlTransformAnnotation(new ClockListTransform)) )
+    .maxOccurs(1)
+    .text("List which signal drives each clock of every descendent of specified module")
+
   def passSeq(top: String, writer: Writer): Seq[Pass] =
     Seq(new ClockList(top, writer))
   def execute(state: CircuitState): CircuitState = {
-- 
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