From 734e3e462ce74178147d5d6b0b6bdc5557f41103 Mon Sep 17 00:00:00 2001
From: Kevin Laeufer
Date: Wed, 29 Jul 2020 13:09:15 -0700
Subject: InferTypes: fix bugs with unknown widths on ports and memories
 (#1769)

* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows

* Don't use passes sub-package in tests

This changes two test files using the "passes" sub-package to
"firrtl.passes". This allows a new "firrtlTests.passes" package to be
freely created and used without a name collision.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* ResolveFlows: only depends on types and working ir

The types are needed to know the orientation of
a bundle field of a SubField node.

* InferTypes: fix bugs with unknown widths on ports and memories

* LoweringCompileSpec: Uniquify pass moved

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/main/scala/firrtl/passes/InferTypes.scala   | 15 ++++++++++-----
 src/main/scala/firrtl/passes/ResolveFlows.scala |  5 +----
 2 files changed, 11 insertions(+), 9 deletions(-)

(limited to 'src/main/scala')

diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala
index 5524e0ea..6cc9f2b9 100644
--- a/src/main/scala/firrtl/passes/InferTypes.scala
+++ b/src/main/scala/firrtl/passes/InferTypes.scala
@@ -20,7 +20,6 @@ object InferTypes extends Pass {
 
   def run(c: Circuit): Circuit = {
     val namespace = Namespace()
-    val mtypes = (c.modules map (m => m.name -> module_type(m))).toMap
 
     def remove_unknowns_b(b: Bound): Bound = b match {
       case UnknownBound => VarBound(namespace.newName("b"))
@@ -40,6 +39,11 @@ object InferTypes extends Pass {
       }
     }
 
+    // we first need to remove the unknown widths and bounds from all ports,
+    // as their type will determine the module types
+    val portsKnown = c.modules.map(_.map{ p: Port => p.copy(tpe = remove_unknowns(p.tpe)) })
+    val mtypes = portsKnown.map(m => m.name -> module_type(m)).toMap
+
     def infer_types_e(types: TypeLookup)(e: Expression): Expression =
       e map infer_types_e(types) match {
         case e: WRef => e copy (tpe = types(e.name))
@@ -71,9 +75,10 @@ object InferTypes extends Pass {
         types(sx.name) = t
         sx copy (tpe = t) map infer_types_e(types)
       case sx: DefMemory =>
-        val t = remove_unknowns(MemPortUtils.memType(sx))
-        types(sx.name) = t
-        sx copy (dataType = remove_unknowns(sx.dataType))
+        // we need to remove the unknowns from the data type so that all ports get the same VarWidth
+        val knownDataType = sx.copy(dataType = remove_unknowns(sx.dataType))
+        types(sx.name) = MemPortUtils.memType(knownDataType)
+        knownDataType
       case sx => sx map infer_types_s(types) map infer_types_e(types)
     }
 
@@ -88,7 +93,7 @@ object InferTypes extends Pass {
       m map infer_types_p(types) map infer_types_s(types)
     }
 
-    c copy (modules = c.modules map infer_types)
+    c.copy(modules = portsKnown.map(infer_types))
   }
 }
 
diff --git a/src/main/scala/firrtl/passes/ResolveFlows.scala b/src/main/scala/firrtl/passes/ResolveFlows.scala
index c3455327..85a0a26f 100644
--- a/src/main/scala/firrtl/passes/ResolveFlows.scala
+++ b/src/main/scala/firrtl/passes/ResolveFlows.scala
@@ -9,10 +9,7 @@ import firrtl.options.Dependency
 
 object ResolveFlows extends Pass {
 
-  override def prerequisites =
-    Seq( Dependency(passes.ResolveKinds),
-         Dependency(passes.InferTypes),
-         Dependency(passes.Uniquify) ) ++ firrtl.stage.Forms.WorkingIR
+  override def prerequisites = Seq(Dependency(passes.InferTypes)) ++ firrtl.stage.Forms.WorkingIR
 
   override def invalidates(a: Transform) = false
 
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