From f04a18efdf4ca88fe1ac77acab30e21290957919 Mon Sep 17 00:00:00 2001
From: Edward Wang
Date: Thu, 21 Sep 2017 16:36:31 -0700
Subject: Some ScalaDoc warning fixes

---
 .../scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/tutorial/lesson1-circuit-traversal')

diff --git a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
index ccd6d9c0..6df6733d 100644
--- a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
@@ -12,7 +12,7 @@ import firrtl.Mappers._
 // Scala's mutable collections
 import scala.collection.mutable
 
-/** Ledger tracks [[Circuit]] statistics
+/** Ledger tracks [[firrtl.ir.Circuit]] statistics
   *
   * In this lesson, we want to count the number of muxes in each
   *  module in our design.
@@ -47,7 +47,7 @@ class Ledger {
 
 /** AnalyzeCircuit Transform
   *
-  * Walks [[ir.Circuit]], and records the number of muxes it finds, per module.
+  * Walks [[firrtl.ir.Circuit]], and records the number of muxes it finds, per module.
   *
   * While some compiler frameworks operate on graphs, we represent a Firrtl
   * circuit using a tree representation:
-- 
cgit v1.2.3