From 1afa3b40f78d781ca1f242b49ca3a56d6cbc57e4 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Mon, 5 Apr 2021 12:18:49 -0700
Subject: Establish a fixed relative order for FPGA-backed passes + reflect in
 ScalaDoc

---
 src/main/scala/firrtl/transforms/SimplifyMems.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/main/scala/firrtl/transforms')

diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala
index 81c40dd4..92e19f7e 100644
--- a/src/main/scala/firrtl/transforms/SimplifyMems.scala
+++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala
@@ -6,6 +6,7 @@ package transforms
 import firrtl.ir._
 import firrtl.Mappers._
 import firrtl.annotations._
+import firrtl.options.Dependency
 import firrtl.passes._
 import firrtl.passes.memlib._
 import firrtl.stage.Forms
@@ -21,7 +22,7 @@ import ResolveMaskGranularity._
 class SimplifyMems extends Transform with DependencyAPIMigration {
 
   override def prerequisites = Forms.MidForm
-  override def optionalPrerequisites = Seq.empty
+  override def optionalPrerequisites = Seq(Dependency[InferReadWrite])
   override def optionalPrerequisiteOf = Forms.MidEmitters
   override def invalidates(a: Transform) = a match {
     case InferTypes => true
-- 
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