From 9624121164e0c65f7ce81048a8c0621882f1d55b Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 1 May 2020 12:58:43 -0700
Subject: Add LegalizeAndReductionsTransform

Workaround for https://github.com/verilator/verilator #2300
present in Verilator versions v4.026 - v4.032. This transform turns AND
reductions for expressions > 64-bits into an equality check with all
ones. It is included as a prerequisite for all Verilog emitters.
---
 .../firrtl/transforms/LegalizeReductions.scala     | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 src/main/scala/firrtl/transforms/LegalizeReductions.scala

(limited to 'src/main/scala/firrtl/transforms')

diff --git a/src/main/scala/firrtl/transforms/LegalizeReductions.scala b/src/main/scala/firrtl/transforms/LegalizeReductions.scala
new file mode 100644
index 00000000..9446c896
--- /dev/null
+++ b/src/main/scala/firrtl/transforms/LegalizeReductions.scala
@@ -0,0 +1,49 @@
+package firrtl
+package transforms
+
+import firrtl.ir._
+import firrtl.Mappers._
+import firrtl.options.{Dependency, PreservesAll}
+import firrtl.Utils.BoolType
+
+
+object LegalizeAndReductionsTransform {
+
+  private def allOnesOfType(tpe: Type): Literal = tpe match {
+    case UIntType(width @ IntWidth(x)) => UIntLiteral((BigInt(1) << x.toInt) - 1, width)
+    case SIntType(width) => SIntLiteral(-1, width)
+
+  }
+
+  def onExpr(expr: Expression): Expression = expr.map(onExpr) match {
+    case DoPrim(PrimOps.Andr, Seq(arg), _,_) if bitWidth(arg.tpe) > 64 =>
+      DoPrim(PrimOps.Eq, Seq(arg, allOnesOfType(arg.tpe)), Seq(), BoolType)
+    case other => other
+  }
+
+  def onStmt(stmt: Statement): Statement = stmt.map(onStmt).map(onExpr)
+
+  def onMod(mod: DefModule): DefModule = mod.map(onStmt)
+}
+
+/** Turns andr for expression > 64-bit into equality check with all ones
+  *
+  * Workaround a bug in Verilator v4.026 - v4.032 (inclusive).
+  * For context, see https://github.com/verilator/verilator/issues/2300
+  */
+class LegalizeAndReductionsTransform extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+
+  override def prerequisites =
+    firrtl.stage.Forms.WorkingIR ++
+    Seq( Dependency(passes.CheckTypes),
+         Dependency(passes.CheckWidths))
+
+  override def optionalPrerequisites = Nil
+
+  override def optionalPrerequisiteOf = Nil
+
+  def execute(state: CircuitState): CircuitState = {
+    val modulesx = state.circuit.modules.map(LegalizeAndReductionsTransform.onMod(_))
+    state.copy(circuit = state.circuit.copy(modules = modulesx))
+  }
+}
-- 
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