From b25cd542192132161f3c162f7e782a9cbb2d09ae Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 16 Jul 2020 17:27:52 -0700 Subject: Propagate source locators to register update always blocks (#1743) * [WIP] Propagate source locators to Verilog if-else emission * Add and fix tests for reg update info propagation * Add limited source locator propagation in ConstProp Support propagating source locators on connections or nodes where the right-hand side is simply a reference. This case comes up a lot for registers without a synchronous reset. node _T_1 = x @[MyFile.scala 12:10] node _T_2 = _T_1 z <= x Previousy the source locator would be lost, now the result is: z <= x @[MyFile.scala 12:10] * Address review comments Co-authored-by: Schuyler Eldridge Co-authored-by: Schuyler Eldridge Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>--- src/main/scala/firrtl/transforms/RemoveReset.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/main/scala/firrtl/transforms/RemoveReset.scala') diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala index 2db93626..6b3a9d07 100644 --- a/src/main/scala/firrtl/transforms/RemoveReset.scala +++ b/src/main/scala/firrtl/transforms/RemoveReset.scala @@ -30,7 +30,7 @@ object RemoveReset extends Transform with DependencyAPIMigration { case _ => false } - private case class Reset(cond: Expression, value: Expression) + private case class Reset(cond: Expression, value: Expression, info: Info) /** Return an immutable set of all invalid expressions in a module * @param m a module @@ -58,14 +58,16 @@ object RemoveReset extends Transform with DependencyAPIMigration { reg.copy(reset = Utils.zero, init = WRef(reg)) case reg @ DefRegister(_, rname, _, _, Utils.zero, _) => reg.copy(init = WRef(reg)) // canonicalize - case reg @ DefRegister(_, rname, _, _, reset, init) if reset.tpe != AsyncResetType => + case reg @ DefRegister(info , rname, _, _, reset, init) if reset.tpe != AsyncResetType => // Add register reset to map - resets(rname) = Reset(reset, init) + resets(rname) = Reset(reset, init, info) reg.copy(reset = Utils.zero, init = WRef(reg)) case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if resets.contains(rname) => val reset = resets(rname) val muxType = Utils.mux_type_and_widths(reset.value, expr) - Connect(info, ref, Mux(reset.cond, reset.value, expr, muxType)) + // Use reg source locator for mux enable and true value since that's where they're defined + val infox = MultiInfo(reset.info, reset.info, info) + Connect(infox, ref, Mux(reset.cond, reset.value, expr, muxType)) case other => other map onStmt } } -- cgit v1.2.3