From 3b22cea87c9d5977c1f7a797091208034dbb8f2e Mon Sep 17 00:00:00 2001
From: Kevin Laeufer
Date: Tue, 28 Jul 2020 09:40:35 -0700
Subject: [2.13] convert toSeq and toMap where necessary to compile

---
 src/main/scala/firrtl/proto/FromProto.scala | 38 +++++++++++++++--------------
 1 file changed, 20 insertions(+), 18 deletions(-)

(limited to 'src/main/scala/firrtl/proto')

diff --git a/src/main/scala/firrtl/proto/FromProto.scala b/src/main/scala/firrtl/proto/FromProto.scala
index 891dc2ba..dced9c2d 100644
--- a/src/main/scala/firrtl/proto/FromProto.scala
+++ b/src/main/scala/firrtl/proto/FromProto.scala
@@ -8,7 +8,9 @@ import java.io.{File, FileInputStream, InputStream}
 import collection.JavaConverters._
 import FirrtlProtos._
 import com.google.protobuf.CodedInputStream
-import Firrtl.Statement.{ReadUnderWrite, Formal}
+import Firrtl.Statement.{Formal, ReadUnderWrite}
+
+import scala.collection.mutable
 
 object FromProto {
 
@@ -34,10 +36,10 @@ object FromProto {
   }
 
   // Convert from ProtoBuf message repeated Statements to FIRRRTL Block
-  private def compressStmts(stmts: Seq[ir.Statement]): ir.Statement = stmts match {
-    case Seq() => ir.EmptyStmt
-    case Seq(stmt) => stmt
-    case multiple => ir.Block(multiple)
+  private def compressStmts(stmts: mutable.Seq[ir.Statement]): ir.Statement = stmts match {
+    case mutable.Seq() => ir.EmptyStmt
+    case mutable.Seq(stmt) => stmt
+    case multiple => ir.Block(multiple.toSeq)
   }
 
   def convert(info: Firrtl.SourceInfo): ir.Info =
@@ -86,8 +88,8 @@ object FromProto {
     ir.SubAccess(convert(access.getExpression), convert(access.getIndex), ir.UnknownType)
 
   def convert(primop: Firrtl.Expression.PrimOp): ir.DoPrim = {
-    val args = primop.getArgList.asScala.map(convert(_))
-    val consts = primop.getConstList.asScala.map(convert(_))
+    val args = primop.getArgList.asScala.map(convert(_)).toSeq
+    val consts = primop.getConstList.asScala.map(convert(_)).toSeq
     ir.DoPrim(convert(primop.getOp), args, consts, ir.UnknownType)
   }
 
@@ -173,7 +175,7 @@ object FromProto {
   }
 
   def convert(printf: Firrtl.Statement.Printf, info: Firrtl.SourceInfo): ir.Print = {
-    val args = printf.getArgList.asScala.map(convert(_))
+    val args = printf.getArgList.asScala.map(convert(_)).toSeq
     val str = ir.StringLit(printf.getValue)
     ir.Print(convert(info), str, args, convert(printf.getClk), convert(printf.getEn))
   }
@@ -193,9 +195,9 @@ object FromProto {
 
   def convert(mem: Firrtl.Statement.Memory, info: Firrtl.SourceInfo): ir.DefMemory = {
     val dtype = convert(mem.getType)
-    val rs = mem.getReaderIdList.asScala
-    val ws = mem.getWriterIdList.asScala
-    val rws = mem.getReadwriterIdList.asScala
+    val rs = mem.getReaderIdList.asScala.toSeq
+    val ws = mem.getWriterIdList.asScala.toSeq
+    val rws = mem.getReadwriterIdList.asScala.toSeq
     import Firrtl.Statement.Memory._
     val depth = mem.getDepthCase.getNumber match {
       case UINT_DEPTH_FIELD_NUMBER => BigInt(mem.getUintDepth)
@@ -206,7 +208,7 @@ object FromProto {
   }
 
   def convert(attach: Firrtl.Statement.Attach, info: Firrtl.SourceInfo): ir.Attach = {
-    val exprs = attach.getExpressionList.asScala.map(convert(_))
+    val exprs = attach.getExpressionList.asScala.map(convert(_)).toSeq
     ir.Attach(convert(info), exprs)
   }
 
@@ -280,7 +282,7 @@ object FromProto {
       case RESET_TYPE_FIELD_NUMBER => ir.ResetType
       case ANALOG_TYPE_FIELD_NUMBER => convert(tpe.getAnalogType)
       case BUNDLE_TYPE_FIELD_NUMBER =>
-        ir.BundleType(tpe.getBundleType.getFieldList.asScala.map(convert(_)))
+        ir.BundleType(tpe.getBundleType.getFieldList.asScala.map(convert(_)).toSeq)
       case VECTOR_TYPE_FIELD_NUMBER => convert(tpe.getVectorType)
     }
   }
@@ -311,16 +313,16 @@ object FromProto {
 
   def convert(module: Firrtl.Module.UserModule): ir.Module = {
     val name = module.getId
-    val ports = module.getPortList.asScala.map(convert(_))
-    val stmts = module.getStatementList.asScala.map(convert(_))
+    val ports = module.getPortList.asScala.map(convert(_)).toSeq
+    val stmts = module.getStatementList.asScala.map(convert(_)).toSeq
     ir.Module(ir.NoInfo, name, ports, ir.Block(stmts))
   }
 
   def convert(module: Firrtl.Module.ExternalModule): ir.ExtModule = {
     val name = module.getId
-    val ports = module.getPortList.asScala.map(convert(_))
+    val ports = module.getPortList.asScala.map(convert(_)).toSeq
     val defname = module.getDefinedName
-    val params = module.getParameterList.asScala.map(convert(_))
+    val params = module.getParameterList.asScala.map(convert(_)).toSeq
     ir.ExtModule(ir.NoInfo, name, ports, defname, params)
   }
 
@@ -335,7 +337,7 @@ object FromProto {
     require(proto.getCircuitCount == 1, "Only 1 circuit is currently supported")
     val c = proto.getCircuit(0)
     require(c.getTopCount == 1, "Only 1 top is currently supported")
-    val modules = c.getModuleList.asScala.map(convert(_))
+    val modules = c.getModuleList.asScala.map(convert(_)).toSeq
     val top = c.getTop(0).getName
     ir.Circuit(ir.NoInfo, modules, top)
   }
-- 
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