From ef8f06f23b9ee6cf86de2450752dfd0fcd32da80 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 22 Apr 2019 21:20:08 -0400 Subject: Add ShellOption, DeletedWrapper Abstracts away option writing such that users no longer have to understand scopt semantics. This adds a ShellOption class and a HasShellOptions trait for something which provides one or more ShellOptions. This refactors the FIRRTL codebase to use this style of option specification. Adds and uses DeletedWrapper to automatically generate DeletedAnnotations. Signed-off-by: Schuyler Eldridge --- .../scala/firrtl/passes/memlib/InferReadWrite.scala | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'src/main/scala/firrtl/passes/memlib/InferReadWrite.scala') diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index f524d60b..0602e4f1 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -8,7 +8,7 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.Utils.{one, zero, BoolType} -import firrtl.options.HasScoptOptions +import firrtl.options.{HasShellOptions, ShellOption} import MemPortUtils.memPortField import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq @@ -147,17 +147,16 @@ object InferReadWritePass extends Pass { // Transform input: Middle Firrtl. Called after "HighFirrtlToMidleFirrtl" // To use this transform, circuit name should be annotated with its TransId. -class InferReadWrite extends Transform with SeqTransformBased with HasScoptOptions { +class InferReadWrite extends Transform with SeqTransformBased with HasShellOptions { def inputForm = MidForm def outputForm = MidForm - def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser - .opt[Unit]("infer-rw") - .abbr("firw") - .valueName ("") - .action( (_, c) => Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)) ++ c ) - .maxOccurs(1) - .text("Enable readwrite port inference for the target circuit") + val options = Seq( + new ShellOption[Unit]( + longOption = "infer-rw", + toAnnotationSeq = (_: Unit) => Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)), + helpText = "Enable read/write port inference for memories", + shortOption = Some("firw") ) ) def transforms = Seq( InferReadWritePass, -- cgit v1.2.3