From 39d76a02785f4391b67abd3b7d7720d287736312 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 21 Apr 2020 22:41:23 -0400 Subject: Mixin DependencyAPIMigration to all Transforms This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge --- .../scala/firrtl/passes/memlib/InferReadWrite.scala | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'src/main/scala/firrtl/passes/memlib/InferReadWrite.scala') diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 1e88a9b0..0de2f46d 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -8,12 +8,12 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.Utils.{one, zero, BoolType} -import firrtl.options.{HasShellOptions, ShellOption} +import firrtl.options.{HasShellOptions, PreservesAll, ShellOption} import MemPortUtils.memPortField import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq import annotations._ -import firrtl.stage.RunFirrtlTransformAnnotation +import firrtl.stage.{Forms, RunFirrtlTransformAnnotation} case object InferReadWriteAnnotation extends NoTargetAnnotation @@ -144,9 +144,15 @@ object InferReadWritePass extends Pass { // Transform input: Middle Firrtl. Called after "HighFirrtlToMidleFirrtl" // To use this transform, circuit name should be annotated with its TransId. -class InferReadWrite extends Transform with SeqTransformBased with HasShellOptions { - def inputForm = MidForm - def outputForm = MidForm +class InferReadWrite extends Transform + with DependencyAPIMigration + with PreservesAll[Transform] + with SeqTransformBased + with HasShellOptions { + + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.MidEmitters val options = Seq( new ShellOption[Unit]( @@ -166,7 +172,7 @@ class InferReadWrite extends Transform with SeqTransformBased with HasShellOptio val runTransform = state.annotations.contains(InferReadWriteAnnotation) if (runTransform) { val ret = runTransforms(state) - CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames) + state.copy(circuit = ret.circuit, annotations = ret.annotations, renames = ret.renames) } else { state } -- cgit v1.2.3