From 6fc742bfaf5ee508a34189400a1a7dbffe3f1cac Mon Sep 17 00:00:00 2001
From: chick
Date: Fri, 14 Aug 2020 19:47:53 -0700
Subject: All of src/ formatted with scalafmt

---
 src/main/scala/firrtl/passes/Legalize.scala | 31 +++++++++++++++--------------
 1 file changed, 16 insertions(+), 15 deletions(-)

(limited to 'src/main/scala/firrtl/passes/Legalize.scala')

diff --git a/src/main/scala/firrtl/passes/Legalize.scala b/src/main/scala/firrtl/passes/Legalize.scala
index 8b7b733a..5d59e075 100644
--- a/src/main/scala/firrtl/passes/Legalize.scala
+++ b/src/main/scala/firrtl/passes/Legalize.scala
@@ -1,11 +1,11 @@
 package firrtl.passes
 
 import firrtl.PrimOps._
-import firrtl.Utils.{BoolType, error, zero}
+import firrtl.Utils.{error, zero, BoolType}
 import firrtl.ir._
 import firrtl.options.Dependency
 import firrtl.transforms.ConstantPropagation
-import firrtl.{Transform, bitWidth}
+import firrtl.{bitWidth, Transform}
 import firrtl.Mappers._
 
 // Replace shr by amount >= arg width with 0 for UInts and MSB for SInts
@@ -62,30 +62,31 @@ object Legalize extends Pass {
     } else {
       val bits = DoPrim(Bits, Seq(c.expr), Seq(w - 1, 0), UIntType(IntWidth(w)))
       val expr = t match {
-        case UIntType(_) => bits
-        case SIntType(_) => DoPrim(AsSInt, Seq(bits), Seq(), SIntType(IntWidth(w)))
+        case UIntType(_)               => bits
+        case SIntType(_)               => DoPrim(AsSInt, Seq(bits), Seq(), SIntType(IntWidth(w)))
         case FixedType(_, IntWidth(p)) => DoPrim(AsFixedPoint, Seq(bits), Seq(p), t)
       }
       Connect(c.info, c.loc, expr)
     }
   }
-  def run (c: Circuit): Circuit = {
-    def legalizeE(expr: Expression): Expression = expr map legalizeE match {
-      case prim: DoPrim => prim.op match {
-        case Shr => legalizeShiftRight(prim)
-        case Pad => legalizePad(prim)
-        case Bits | Head | Tail => legalizeBitExtract(prim)
-        case _ => prim
-      }
+  def run(c: Circuit): Circuit = {
+    def legalizeE(expr: Expression): Expression = expr.map(legalizeE) match {
+      case prim: DoPrim =>
+        prim.op match {
+          case Shr                => legalizeShiftRight(prim)
+          case Pad                => legalizePad(prim)
+          case Bits | Head | Tail => legalizeBitExtract(prim)
+          case _                  => prim
+        }
       case e => e // respect pre-order traversal
     }
-    def legalizeS (s: Statement): Statement = {
+    def legalizeS(s: Statement): Statement = {
       val legalizedStmt = s match {
         case c: Connect => legalizeConnect(c)
         case _ => s
       }
-      legalizedStmt map legalizeS map legalizeE
+      legalizedStmt.map(legalizeS).map(legalizeE)
     }
-    c copy (modules = c.modules map (_ map legalizeS))
+    c.copy(modules = c.modules.map(_.map(legalizeS)))
   }
 }
-- 
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