From bb5f68948c6d75d1f02c614f3e0ae4ef9bc6e689 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 9 Feb 2016 14:48:12 -0800
Subject: Added remaining check passes. Ready for open sourcing

---
 src/main/scala/firrtl/Visitor.scala | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/firrtl/Visitor.scala')

diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 76759687..3fe8c176 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -57,7 +57,10 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
     Circuit(getInfo(ctx), ctx.module.map(visitModule), (ctx.id.getText)) 
     
   private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): Module = 
-    InModule(getInfo(ctx), (ctx.id.getText), ctx.port.map(visitPort), visitBlock(ctx.block))
+     ctx.getChild(0).getText match {
+        case "module" => InModule(getInfo(ctx), (ctx.id.getText), ctx.port.map(visitPort), visitBlock(ctx.block))
+        case "extmodule" => ExModule(getInfo(ctx), (ctx.id.getText), ctx.port.map(visitPort))
+      }
 
   private def visitPort[AST](ctx: FIRRTLParser.PortContext): Port = 
     Port(getInfo(ctx), (ctx.id.getText), visitDir(ctx.dir), visitType(ctx.`type`))
@@ -206,7 +209,7 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
               (IntWidth(string2BigInt(ctx.IntLit(0).getText)), string2BigInt(ctx.IntLit(1).getText))
             else {
                val bigint = string2BigInt(ctx.IntLit(0).getText)
-               (IntWidth(BigInt(bigint.bitLength)),bigint)
+               (IntWidth(BigInt(scala.math.max(bigint.bitLength,1))),bigint)
             }
           UIntValue(value, width)
         }
-- 
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