From c19a53a562883ebb7d9c6131c4ef308bcfbd720a Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 7 Nov 2016 20:36:19 -0500
Subject: Clock List Transform (#365)

Added clocklist transform---
 src/main/scala/firrtl/ExecutionOptionsManager.scala | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/main/scala/firrtl/ExecutionOptionsManager.scala')

diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala
index ae0636d9..704992c2 100644
--- a/src/main/scala/firrtl/ExecutionOptionsManager.scala
+++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala
@@ -5,6 +5,7 @@ package firrtl
 import firrtl.Annotations._
 import firrtl.Parser._
 import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation}
+import firrtl.passes.clocklist.ClockListAnnotation
 import logger.LogLevel
 import scopt.OptionParser
 
@@ -291,6 +292,19 @@ trait HasFirrtlOptions {
       "Replace sequential memories with blackboxes + configuration file"
     }
 
+  parser.opt[String]("list-clocks")
+    .abbr("clks")
+    .valueName ("-c:<circuit>:-m:<module>:-o:<filename>")
+    .foreach { x =>
+      firrtlOptions = firrtlOptions.copy(
+        annotations = firrtlOptions.annotations :+ ClockListAnnotation(x),
+        customTransforms = firrtlOptions.customTransforms :+ new passes.clocklist.ClockListTransform
+      )
+    }
+    .text {
+      "List which signal drives each clock of every descendent of specified module"
+    }
+
   parser.note("")
 
 }
-- 
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