From 0d5fa689a45693bf6db9bc6d9dc3f150bc3ff4b8 Mon Sep 17 00:00:00 2001
From: Angie
Date: Fri, 19 Aug 2016 17:00:11 -0700
Subject: Added starter code for SMem replacement

---
 src/main/scala/firrtl/Driver.scala | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src/main/scala/firrtl/Driver.scala')

diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 5969562f..79f2fdaf 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -57,6 +57,12 @@ Optional Arguments:
                                  Supported modes: ignore, use, gen, append
   --inferRW <circuit>            Enable readwrite port inference for the target circuit
   --inline <module>|<instance>   Inline a module (e.g. "MyModule") or instance (e.g. "MyModule.myinstance")
+
+  --replSeqMem -c:<circuit>:-i<filename>:-o<filename> 
+  *** Replace sequential memories with blackboxes + configuration file
+  *** Input configuration file optional
+  *** Note: sub-arguments to --replSeqMem should be delimited by : and not white space!
+  
   [--help|-h]                    Print usage string
 """
 
@@ -74,12 +80,16 @@ Optional Arguments:
     def handleInferRWOption(value: String) = 
       passes.InferReadWriteAnnotation(value, TransID(-1))
 
+    def handleReplSeqMem(value: String) = 
+      passes.ReplSeqMemAnnotation(value, TransID(-2))
+
     run(args: Array[String],
       Map( "high" -> new HighFirrtlCompiler(),
         "low" -> new LowFirrtlCompiler(),
         "verilog" -> new VerilogCompiler()),
       Map("--inline" -> handleInlineOption _,
-          "--inferRW" -> handleInferRWOption _),
+          "--inferRW" -> handleInferRWOption _,
+          "--replSeqMem" -> handleReplSeqMem _),
       usage
     )
   }
-- 
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