From abf226471249a1cbb8de33d0c4bc8526f9aafa70 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 17 Dec 2019 18:29:47 -0500 Subject: Migrate to DependencyAPI Co-authored-by: Schuyler Eldridge Co-authored-by: Albert Magyar Signed-off-by: Schuyler Eldridge --- src/main/scala/firrtl/AddDescriptionNodes.scala | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'src/main/scala/firrtl/AddDescriptionNodes.scala') diff --git a/src/main/scala/firrtl/AddDescriptionNodes.scala b/src/main/scala/firrtl/AddDescriptionNodes.scala index 2cd8b9f7..dac0e513 100644 --- a/src/main/scala/firrtl/AddDescriptionNodes.scala +++ b/src/main/scala/firrtl/AddDescriptionNodes.scala @@ -5,6 +5,7 @@ package firrtl import firrtl.ir._ import firrtl.annotations._ import firrtl.Mappers._ +import firrtl.options.{Dependency, PreservesAll} case class DescriptionAnnotation(named: Named, description: String) extends Annotation { def update(renames: RenameMap): Seq[DescriptionAnnotation] = { @@ -67,9 +68,25 @@ private case class DescribedMod(description: Description, * @note should only be used by VerilogEmitter, described nodes will * break other transforms. */ -class AddDescriptionNodes extends Transform { - def inputForm = LowForm - def outputForm = LowForm +class AddDescriptionNodes extends Transform with PreservesAll[Transform] { + def inputForm = UnknownForm + def outputForm = UnknownForm + + override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper], + Dependency[firrtl.transforms.FixAddingNegativeLiterals], + Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], + Dependency[firrtl.transforms.InlineBitExtractionsTransform], + Dependency[firrtl.transforms.InlineCastsTransform], + Dependency[firrtl.transforms.LegalizeClocksTransform], + Dependency[firrtl.transforms.FlattenRegUpdate], + Dependency(passes.VerilogModulusCleanup), + Dependency[firrtl.transforms.VerilogRename], + Dependency(firrtl.passes.VerilogPrep) ) + + override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + + override val dependents = Seq.empty def onStmt(compMap: Map[String, Seq[String]])(stmt: Statement): Statement = { stmt.map(onStmt(compMap)) match { -- cgit v1.2.3