From e54fb610c6bf0a7fe5c9c0f0e0b3acbb3728cfd0 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Sun, 25 Sep 2016 20:35:09 -0700
Subject: Spec features added: AnalogType and Attach (#295)

* Spec features added: AnalogType and Attach

AnalogType(width: Width):
  - Concrete syntax:
      wire x: AnalogType<10>
  - New groundtype, very restricted in use cases.
  - Can only declare ports and wires with Analog type
  - Analog types are never equivalent, thus if x and y have Analog
    types: x <= y is never legal.

Attach(info: Info, source: Expression, exprs: Seq[Expression]):
  - Concrete syntax:
      attach x to (y, z)
  - New statement
  - Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
  - Exprs must have an Analog type reference an instance port
  - Source and exprs must have identical widths

Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.

* Fixed bug where invalidated ports aren't handled

* Bugfix for VerilogPrep

Intermediate wires for invalidated instance ports were not invalidated

* Bugfix: calling create_exp with name/tpe

Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals

* Addressed donggyukim's style comments

* Reworked pass to only allow analog types in attach

Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)

* Fixup bugs from pulling in new changes from master

* comments for type eqs and small style fixes
---
 src/main/antlr4/FIRRTL.g4 | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/main/antlr4')

diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index ef0fd7eb..1232b65f 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -79,6 +79,7 @@ type
   : 'UInt' ('<' IntLit '>')?
   | 'SInt' ('<' IntLit '>')?
   | 'Clock'
+  | 'Analog' ('<' IntLit '>')?
   | '{' field* '}'        // Bundle
   | type '[' IntLit ']'   // Vector
   ;
@@ -119,6 +120,7 @@ stmt
   | 'stop(' exp exp IntLit ')' info?
   | 'printf(' exp exp StringLit ( exp)* ')' info?
   | 'skip' info?
+  | 'attach' exp 'to' '(' exp* ')' info?
   ;
 
 memField
-- 
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