From 2f4ae9b4164cf415600de970b3ac5a1b9760efa5 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 7 Feb 2017 16:54:35 -0800
Subject: Rework Attach to work on arbitrary Analog hierarchies (#415)

* Rework Attach to work on arbitrary Analog hierarchies

If there are zero or one Analog sources in an Attach (source meaning
wire or parent module port), then the Attach will be emitted as a simple
point to point connection. In the general case, alias is used for
simulation while forwards and backwards assigns for synthesis. Verilator
does not currently support the general case so an `ifdef Verilator
`error is emitted.

* Add helper functions for creating WRef from Reg and Wire
---
 src/main/antlr4/FIRRTL.g4 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/antlr4')

diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index f5bcb685..9e6a46ee 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -108,7 +108,7 @@ stmt
   | 'stop(' exp exp IntLit ')' info?
   | 'printf(' exp exp StringLit ( exp)* ')' info?
   | 'skip' info?
-  | 'attach' exp 'to' '(' exp* ')' info?
+  | 'attach' '(' exp+ ')' info?
   ;
 
 memField
-- 
cgit v1.2.3