From d98526e50f9dee6edd4d885c707972cfa9666e34 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 23 Jan 2016 15:36:09 -0800
Subject: Added inference to mports

---
 spec/spec.tex | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

(limited to 'spec')

diff --git a/spec/spec.tex b/spec/spec.tex
index fff0bbff..be0bae93 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1791,19 +1791,18 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 
 %\section{TODO}
 %
-%- Check sponsor paragraph
-%
 %- FIRRTL implementation
-%   - Make register reset/init optional
-%   - Rework readwrite port types
-%   - Add memory read-under-write flag
-%   - Add partial connect algorithm
+%   - Make register reset/init optional ; good
+%   - Rework readwrite port types       ; limits optimizations but probably ok
+%   - Add memory read-under-write flag  ; probably overengineering, but could be a wash
+%   - Add partial connect algorithm     ; 
 %   - Add oriented types to type checker
-%   - Add is invalid
-%   - Add validif
-%   - Add UBits
+%   - Add is invalid                    ; good
+%   - Add validif                       ; good
+%   - Add UBits                         ; andrew doesn't care, favors overloading UInt
 %   - Add SBits
-%   - Add Mux expression
+%   - Add Mux expression                ; that's lovely, need glitch-free mux for clock types
+%   - removed addw, added head and tail ; great!
 
 \end{document}
 
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