From f711861808e3ca914f71a3089c6879dbcb7dc08d Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 Jan 2016 14:16:09 -0800
Subject: Changed register syntax for optional reset and init values

---
 spec/spec.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'spec')

diff --git a/spec/spec.tex b/spec/spec.tex
index 12f2c91e..7c528467 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1792,7 +1792,6 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %\section{TODO}
 %
 %- FIRRTL implementation
-%   - Rework readwrite port types       ; limits optimizations but probably ok
 %   - Make register reset/init optional ; good
 %   - removed addw, added head and tail ; great!
 %   - Add UBits                         ; andrew doesn't care, favors overloading UInt
@@ -1800,6 +1799,7 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %   - Add partial connect algorithm     ; 
 %   - Add oriented types to type checker
 %   - Add memory read-under-write flag  ; probably overengineering, but could be a wash
+%   - *FINISHED* Rework readwrite port types       ; limits optimizations but probably ok
 %   - *FINISHED* Add Mux expression                ; that's lovely, need glitch-free mux for clock types
 %   - *FINISHED* add rename pass for verilog
 %   - *FINISHED* Add is invalid                    ; good
-- 
cgit v1.2.3


From 5c1f1c18cae31eb53bf09cb58f6ecd6b30e55fb3 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 Jan 2016 11:30:35 -0800
Subject: Updated todo list

---
 spec/spec.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'spec')

diff --git a/spec/spec.tex b/spec/spec.tex
index 7c528467..dc15e1b8 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1792,13 +1792,13 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %\section{TODO}
 %
 %- FIRRTL implementation
-%   - Make register reset/init optional ; good
-%   - removed addw, added head and tail ; great!
 %   - Add UBits                         ; andrew doesn't care, favors overloading UInt
 %   - Add SBits
 %   - Add partial connect algorithm     ; 
 %   - Add oriented types to type checker
 %   - Add memory read-under-write flag  ; probably overengineering, but could be a wash
+%   - *FINISHED* Make register reset/init optional ; good
+%   - *FINISHED* removed addw, added head and tail ; great!
 %   - *FINISHED* Rework readwrite port types       ; limits optimizations but probably ok
 %   - *FINISHED* Add Mux expression                ; that's lovely, need glitch-free mux for clock types
 %   - *FINISHED* add rename pass for verilog
-- 
cgit v1.2.3


From 4bf3a3dd73108186807dee603794579fa88ccf50 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 Jan 2016 12:13:25 -0800
Subject: Changed mod to rem

---
 spec/spec.tex | 1 +
 1 file changed, 1 insertion(+)

(limited to 'spec')

diff --git a/spec/spec.tex b/spec/spec.tex
index dc15e1b8..b8b1fd55 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1808,6 +1808,7 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %- Proposed changes to spec
 %   - switch back to precise dynamic left shift
 %   - have a wmode instead of rmode for readwrite ports
+%   - rename mod to rem
 
 \end{document}
 
-- 
cgit v1.2.3


From cfedffd1fc7d5846e9f633bf13ea194b8ab2293d Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 Jan 2016 15:59:48 -0800
Subject: Changed rmode to wmode

---
 spec/spec.tex | 1 +
 1 file changed, 1 insertion(+)

(limited to 'spec')

diff --git a/spec/spec.tex b/spec/spec.tex
index b8b1fd55..ae633ecc 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1809,6 +1809,7 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %   - switch back to precise dynamic left shift
 %   - have a wmode instead of rmode for readwrite ports
 %   - rename mod to rem
+%   - changed rmode to wmode
 
 \end{document}
 
-- 
cgit v1.2.3