From eeb565de1005927bcfd7bde15bd1d4e09394cb78 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 25 Jan 2016 15:59:59 -0800
Subject: Added verilog rename pass

---
 spec/spec.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'spec/spec.tex')

diff --git a/spec/spec.tex b/spec/spec.tex
index aaf2577d..93d62525 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1797,8 +1797,8 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %   - Add memory read-under-write flag  ; probably overengineering, but could be a wash
 %   - Add partial connect algorithm     ; 
 %   - Add oriented types to type checker
-%   - Add is invalid                    ; good
-%   - Add validif                       ; good
+%   - *FINISHED* Add is invalid                    ; good
+%   - *FINISHED* Add validif                       ; good
 %   - Add UBits                         ; andrew doesn't care, favors overloading UInt
 %   - Add SBits
 %   - *FINISHED* Add Mux expression                ; that's lovely, need glitch-free mux for clock types
-- 
cgit v1.2.3

