From c140b1ffbcf7fb5b2bb05e93388b2c79f2ddf9f9 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 13 Apr 2015 17:51:00 -0700
Subject: Finished Infer Widths

---
 notes/chisel.04.13.15.txt | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 notes/chisel.04.13.15.txt

(limited to 'notes')

diff --git a/notes/chisel.04.13.15.txt b/notes/chisel.04.13.15.txt
new file mode 100644
index 00000000..b9a1d099
--- /dev/null
+++ b/notes/chisel.04.13.15.txt
@@ -0,0 +1,29 @@
+Std Library Discussion
+
+FIRRTL Feedback:
+   Can we write an asynchronous FIFO using our implicit clock port semantics? (Patrick)
+      Unclear.
+
+   Can't mux between Bundle Types. (Stephen)
+      We think that is ok.
+
+   Bit-wise operation on SInts. Knocking down low bits. (Stephen)
+      Good point, we can define these.
+
+   UInt - UInt = SInt
+      ...
+
+   cmem vs reg of vec?
+      reg of vec has initialization, and can be accessed combinationally
+      maybe
+
+   subword updates?
+      modeled through the bundle types
+      not supported, but need to figure out how to support it
+
+   printfs and asserts
+
+   all primops require same widths. Need explicit incrementer node.
+
+   add padTo
+
-- 
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