From 95dd261b4e65840ade351dcb00e4164a99daf654 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 20 Feb 2015 16:56:25 -0800
Subject: Rewrote the initialize-register pass, now correctly implemented with
 a new IR construct - Null. LetRec is not implemented, but is marked with a
 TODO.

Test cases for this pass are now located in
test/passes/initialize-register
---
 notes/initialize-register-explanation.txt | 81 +++++++++++++++++++++++++++++++
 notes/stanza-cheatsheet.txt               |  9 ++++
 2 files changed, 90 insertions(+)
 create mode 100644 notes/initialize-register-explanation.txt

(limited to 'notes')

diff --git a/notes/initialize-register-explanation.txt b/notes/initialize-register-explanation.txt
new file mode 100644
index 00000000..27bbde52
--- /dev/null
+++ b/notes/initialize-register-explanation.txt
@@ -0,0 +1,81 @@
+reg r: UInt(16)
+
+=>
+
+reg r: UInt(16)
+wire r_init : UInt(16)
+r_init := NULL
+
+when reset :
+   r := r_init
+
+===============
+
+reg r: UInt(16)
+r.init := UInt(0)
+
+=>
+
+reg r: UInt(16)
+wire r_init : UInt(16)
+r_init := NULL
+r_init := UInt(0)
+when reset :
+   r := r_init
+
+=>
+
+reg r: UInt(16)
+wire r_init2 : UInt(16)
+r_init2 := NULL
+wire r_init : UInt(16)
+r_init := NULL
+r_init := UInt(0)
+when reset :
+   r := r_init
+when reset :
+   r := r_init2
+
+
+======
+
+We continue to simplify from the previous example. Here's the input we had (but with the incorrect lines removed).
+
+reg r: UInt(16)
+wire r_init2 : UInt(16)
+r_init2 := NULL
+wire r_init : UInt(16)
+r_init := NULL
+r_init := UInt(0)
+when reset :
+   r := r_init
+when reset :
+   r := r_init2
+
+One of the following passes will turn wires into nodes, by scanning to see what they are connected to.
+
+reg r: UInt(16)
+node r_init2 = NULL
+node r_init = UInt(0)
+when reset :
+   r := r_init
+when reset :
+   r := r_init2
+
+Another pass will compute the final value connected to the register, expressed as a bunch of muxes. The default value for a register is set to itself.
+
+node r_init2 = NULL
+node r_init = UInt(0)
+reg r:UInt(16) = Mux(reset, r_init2, Mux(reset, r_init, r))
+
+Next we inline all the nodes with NULL in them, to arrive at the final expression for the register.
+
+reg r:UInt(16) = Mux(reset, NULL, Mux(reset, r_init, r))
+
+NULL's do nothing, so any expression of the form Mux(a, NULL, b) can be simplified to b. Arriving finally at:
+
+reg r:UInt(16) = Mux(reset, r_init, r)
+
+which is what we wanted. 
+
+
diff --git a/notes/stanza-cheatsheet.txt b/notes/stanza-cheatsheet.txt
index d8f5c070..09342997 100644
--- a/notes/stanza-cheatsheet.txt
+++ b/notes/stanza-cheatsheet.txt
@@ -46,3 +46,12 @@ a typeof T
 a and b
 a or b
 a as T
+
+
+append(list1,list2) -> list1,list2
+List(x,list) -> x,list
+list() -> empty
+list(a) -> a
+list(a,b) -> a,b 
+
+println-all([a b c])
-- 
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