From eb5ca3c967c929c8331fd17e04dbd9402e41e986 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 2 Jun 2015 15:35:02 -0700
Subject: Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve
 correct low-firrtl syntax. Generates verilog that compiles, but is not
 correct

---
 TODO | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'TODO')

diff --git a/TODO b/TODO
index 31319411..0997c219 100644
--- a/TODO
+++ b/TODO
@@ -48,6 +48,7 @@ High-Firrtl
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
+   Register/ReadPort/WritePort are only in correct spots
 Width inference
    No names
    No Unknowns
@@ -55,6 +56,7 @@ Width inference
    Pad's width is greater than value's width
    pad's width is greater than value's width
    connect can connect from big to small??
+Width pad check?
 
 ======== Other Passes ========
 constant folding (partial eval) pass
-- 
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