From cfd3149589d03338d1d9735f5c232e89d67767b0 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 4 May 2015 12:42:51 -0700
Subject: Added a few more error checks. Not tested yet. Fixed bug in pad type
 inference

---
 TODO | 1 +
 1 file changed, 1 insertion(+)

(limited to 'TODO')

diff --git a/TODO b/TODO
index d5ff2955..44d194b8 100644
--- a/TODO
+++ b/TODO
@@ -102,6 +102,7 @@ Fast C++ where wires/register/instances are predicated
 Verilog backend - put stuff in posedge clock, not assign statements, for speedup
 Annotate mems with location stuff
 Coverage tests, such as statespace or specific instances (like asserts, sort of)
+   check all predicates of whens
 
 ======== FIRRTL++ =========
 Variable size FIFOs
-- 
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