From 1644ed195522cd7343aaaa047e6669529907de9f Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 28 Apr 2015 17:32:19 -0700
Subject: Instances are now male. Reworked lowering pass to be sane.
 chisel3/ModuleVec.fir doesn't work because incorrecly generated?

---
 TODO | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'TODO')

diff --git a/TODO b/TODO
index fd5685bd..1c84cc96 100644
--- a/TODO
+++ b/TODO
@@ -5,8 +5,9 @@
 ======== Current Tasks ========
 Make instances always male, flip the bundles on declaration
 dlsh,drsh
-move Infer-Widths to before vec expansion?
 Add Unit Tests for each pass
+<>
+Update spec
    
 ======== Update Core ==========
 Add source locaters
@@ -26,6 +27,8 @@ Well-formed high firrtl
    onreset can only handle a register
    all references are declared
    expression in pad must be a ground type
+   node's value cannot be a bundle with a flip in it
+   mems cannot be a bundle with flips
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
@@ -53,6 +56,7 @@ Patrick:
    move Infer-Widths to before vec expansion?
 
 ======== Think About ========
+<>
 subword accesses
 verilog style guide
 naming for split nodes
-- 
cgit v1.2.3


From c46608d92bd493fa33c3c5122341c716ca75ecb0 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 28 Apr 2015 17:32:50 -0700
Subject: Updated todo

---
 TODO | 1 -
 1 file changed, 1 deletion(-)

(limited to 'TODO')

diff --git a/TODO b/TODO
index 1c84cc96..f4747cb4 100644
--- a/TODO
+++ b/TODO
@@ -3,7 +3,6 @@
 ================================================
 
 ======== Current Tasks ========
-Make instances always male, flip the bundles on declaration
 dlsh,drsh
 Add Unit Tests for each pass
 <>
-- 
cgit v1.2.3