From 791334cced721789fad180b6479cfa783963032f Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 5 May 2015 17:37:27 -0700
Subject: Added a bunch of tests. In the middle of implementing check kinds and
 check types. Does not compile

---
 TODO | 1 +
 1 file changed, 1 insertion(+)

(limited to 'TODO')

diff --git a/TODO b/TODO
index 1b5520c8..e2f8b339 100644
--- a/TODO
+++ b/TODO
@@ -108,6 +108,7 @@ Verilog backend - put stuff in posedge clock, not assign statements, for speedup
 Annotate mems with location stuff
 Coverage tests, such as statespace or specific instances (like asserts, sort of)
    check all predicates of whens
+Generate a ROM, and index with cycle counter, and dynamically check any wire on a given cycle
 
 ======== FIRRTL++ =========
 Variable size FIFOs
-- 
cgit v1.2.3


From 2cf26ba655e59937f5a52aa50db2d97538d1fdde Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 13 May 2015 10:42:36 -0700
Subject: Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed
 lowering bug

---
 TODO | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'TODO')

diff --git a/TODO b/TODO
index e2f8b339..2f58ab0d 100644
--- a/TODO
+++ b/TODO
@@ -3,6 +3,9 @@
 ================================================
 
 ======== Current Tasks ========
+Declared references needs to understand scope
+Size of vector type must be non-negative
+Check for recursively defined instances
 Update spec
 <>
 Add Unit Tests for each pass
@@ -10,9 +13,13 @@ Add Unit Tests for each pass
    Push all tests entirely through
    Check after each pass
    write test that checks instance types are correctly lowered
+move width inference earlier
    
 ======== Update Core ==========
 Add source locaters
+Add exmodule
+Add vptype
+Add readwriteport
 
 ======== Check Passes ==========
 Well-formed high firrtl 
@@ -83,7 +90,9 @@ Convert to scala
 Firrtl interpreter (in scala)
 
 ======== Update Spec ========
-Add Not to spec
+Look through all primops
+change parser to other unknown thing for vptype?
+Add optional type to node
 add assertions and printfs
 cannot connect directly to a mem (loc can never contain a mem)
 Front-end needs to guarantee unique names per module.
-- 
cgit v1.2.3


From 521a4277bfc1d764dc9ee771c604200525e871cb Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 13 May 2015 17:08:29 -0700
Subject: Added source indicators from FIRRTL files. Pass in -p i to get them
 printed. Should show up with check passes

---
 TODO | 1 +
 1 file changed, 1 insertion(+)

(limited to 'TODO')

diff --git a/TODO b/TODO
index 2f58ab0d..9a4e7afc 100644
--- a/TODO
+++ b/TODO
@@ -14,6 +14,7 @@ Add Unit Tests for each pass
    Check after each pass
    write test that checks instance types are correctly lowered
 move width inference earlier
+Register should be a NODE, not a wire that is connected to, because you shouldn't be able to write to a wire that was connected to a Register? hmm.. think about this
    
 ======== Update Core ==========
 Add source locaters
-- 
cgit v1.2.3