From 9e32fd0ddfe3510d02ac4f5c2a118b631d4d3d6b Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Mon, 19 Mar 2018 16:08:53 -0700
Subject: Update README.md (#761)

---
 README.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'README.md')

diff --git a/README.md b/README.md
index ce868eb4..39334d1e 100644
--- a/README.md
+++ b/README.md
@@ -11,8 +11,6 @@
 
  For a detailed description of Firrtl's intermediate representation, see the document "Specification of the Firrtl Language" located in [spec/spec.pdf](https://github.com/ucb-bar/firrtl/blob/master/spec/spec.pdf).
 
- This repository is in ALPHA VERSION, so many things may change in the coming months.
-
 #### Wiki Pages and Tutorials
 
 Useful information is on our wiki, located here:
@@ -40,7 +38,7 @@ sbt assembly
 * Yosys Verilog-to-Firrtl Front-end: https://github.com/cliffordwolf/yosys
 
 #### Installation Instructions
-*Disclaimer*: This project is in alpha, so there is no guarantee anything works. The installation instructions should work for OSX/Linux machines.
+*Disclaimer*: The installation instructions should work for OSX/Linux machines. Other environments may not be tested.
 
 ##### Prerequisites
  1. If not already installed, install [verilator](http://www.veripool.org/projects/verilator/wiki/Installing) (Requires at least v3.886)
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