From ff6dfecf42560ed2e2eb678adc9ca8d868a472bd Mon Sep 17 00:00:00 2001 From: azidar Date: Mon, 3 Aug 2015 18:39:55 -0700 Subject: Changed name mangling to use _ as a delin. Fixed bug in checking for invalid <> assignments. --- src/main/stanza/errors.stanza | 31 +- src/main/stanza/firrtl-ir.stanza | 1 + src/main/stanza/firrtl-test-main.stanza | 2 +- src/main/stanza/flo.stanza | 2 +- src/main/stanza/ir-utils.stanza | 76 +++-- src/main/stanza/passes.stanza | 18 +- test/errors/gender/BulkWrong.fir | 2 +- test/errors/gender/bad_bulk_connect.fir | 328 +++++++++++++++++++++ test/errors/type/Primop.fir | 2 - test/features/EmptyStmt.fir | 11 + test/passes/expand-connect-indexed/bundle-vecs.fir | 10 +- test/passes/split-exp/primop.fir | 21 ++ 12 files changed, 460 insertions(+), 44 deletions(-) create mode 100644 test/errors/gender/bad_bulk_connect.fir create mode 100644 test/features/EmptyStmt.fir create mode 100644 test/passes/split-exp/primop.fir diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 2fb1352c..5212bcb5 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -695,7 +695,7 @@ defn InferDirection (info:FileInfo,name:Symbol) : defn dir-to-gender (d:PortDirection) -> Gender : switch {_ == d} : INPUT : MALE - OUTPUT : BI-GENDER + OUTPUT : FEMALE ;BI-GENDER defn gender (s:DefAccessor) -> Gender : switch {_ == acc-dir(s)} : @@ -715,14 +715,28 @@ defn as-srcsnk (g:Gender) -> Symbol : public defn check-genders (c:Circuit) -> Circuit : val errors = Vector() - defn check-gender (info:FileInfo,genders:HashTable,e:Expression,right:Gender) -> False : + defn get-kind (e:Expression) -> Kind : + match(e) : + (e:WRef) : kind(e) + (e:WSubfield) : get-kind(exp(e)) + (e:WIndex) : get-kind(exp(e)) + (e) : NodeKind() + + defn check-gender (info:FileInfo,genders:HashTable,e:Expression,desired:Gender) -> False : val gender = get-gender(e,genders) + val kind* = get-kind(e) + ;println(e) ;println(gender) - ;println(right) - ;println(right == gender) - ;if gender != right and gender != BI-GENDER: - switch fn ([x,y]) : gender == x and right == y : - [MALE, FEMALE] : add(errors,WrongGender(info,to-symbol(e),as-srcsnk(right),as-srcsnk(gender))) + ;println(desired) + ;println(kind*) + ;println(desired == gender) + ;if gender != desired and gender != BI-GENDER: + switch fn ([x,y]) : gender == x and desired == y : + [MALE, FEMALE] : + add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender))) + [FEMALE, MALE] : + if kind* != PortKind() : + add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender))) else : false defn get-gender (e:Expression,genders:HashTable) -> Gender : @@ -730,7 +744,7 @@ public defn check-genders (c:Circuit) -> Circuit : (e:WRef) : genders[name(e)] (e:WSubfield) : val f = {_ as Field} $ for f in fields(type(exp(e)) as BundleType) find : name(f) == name(e) - get-gender(exp(e),genders) * flip(f) + get-gender(exp(e),genders) * flip(f) (e:WIndex) : get-gender(exp(e),genders) (e:DoPrim) : MALE (e:UIntValue) : MALE @@ -787,6 +801,7 @@ public defn check-genders (c:Circuit) -> Circuit : match(m) : (m:ExModule) : false (m:InModule) : check-genders-s(body(m),genders) + println(genders) throw(PassExceptions(errors)) when not empty?(errors) c diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 79057791..e1f91254 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -13,6 +13,7 @@ public val scope-delin = `% public val temp-delin = `! public val sub-delin = `* public val inline-delin = `^ +public val delin = `_ public definterface PortDirection public val INPUT = new PortDirection diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index e5aad984..f22c49f1 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -79,7 +79,7 @@ defn main () : if last-s == "-o" : output = args[i] if last-s == "-x" : add(pass-names,args[i]) if last-s == "-X" : compiler = args[i] - if last-s == "-p" : printvars = args[i] + if last-s == "-p" : printvars = to-string([printvars args[i]]) if last-s == "-s" : add(pass-args,args[i]) if last-s == "-m" : add(firms,args[i]) diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index 7ef942f2..812a917e 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -198,7 +198,7 @@ defn emit-module (m:InModule,sh:HashTable) : public defn emit-flo (with-output:(() -> False) -> False, c:Circuit) : with-output $ { - emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule)) + emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule,v-keywords)) false } c diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index f3fb5a53..2fb92407 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -9,32 +9,74 @@ public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|M ;============== GENSYM STUFF ====================== +public val v-keywords = to-list $ [ + `always, `and, `assign, `attribute, `begin, `buf, `bufif0, `bufif1, + `case, `casex, `casez, `cmos, `deassign, `default, `defparam, + `disable, `edge, `else, `end, `endattribute, `endcase, `endfunction, + `endmodule, `endprimitive, `endspecify, `endtable, `endtask, `event, + `for, `force, `forever, `fork, `function, `highz0, `highz1, `if, + `ifnone, `initial, `inout, `input, `integer, `initvar, `join, + `medium, `module, `large, `macromodule, `nand, `negedge, `nmos, + `nor, `not, `notif0, `notif1, `or, `output, `parameter, `pmos, + `posedge, `primitive, `pull0, `pull1, `pulldown, `pullup, `rcmos, + `real, `realtime, `reg, `release, `repeat, `rnmos, `rpmos, `rtran, + `rtranif0, `rtranif1, `scalared, `signed, `small, `specify, + `specparam, `strength, `strong0, `strong1, `supply0, `supply1, + `table, `task, `time, `tran, `tranif0, `tranif1, `tri, `tri0, + `tri1, `triand, `trior, `trireg, `unsigned, `vectored, `wait, + `wand, `weak0, `weak1, `while, `wire, `wor, `xnor, `xor, + `SYNTHESIS, `PRINTF_COND, `VCS ] public defn firrtl-gensym (s:Symbol) -> Symbol : firrtl-gensym(s,HashTable(symbol-hash)) -public defn firrtl-gensym (s:Symbol,sym-hash:HashTable) -> Symbol : - firrtl-gensym(s,sym-hash,temp-delin) public defn firrtl-gensym (sym-hash:HashTable) -> Symbol : firrtl-gensym(`gen,sym-hash) -public defn firrtl-gensym (s:Symbol,sym-hash:HashTable,delin:Symbol) -> Symbol : - val num = get?(sym-hash,s,0) - sym-hash[s] = num + 1 - symbol-join([s delin num]) - ;defn get-new (s:Symbol, i:Int) -> Symbol : - ; val s* = symbol-join([s i]) - ; if key?(sym-hash,s*) : - ; get-new(s,i + 1) - ; else : - ; sym-hash[s] = i - ; sym-hash[s*] = 0 - ; s* - ;get-new(s,0) - +defn digits? (s:String) -> True|False : + val digits = "0123456789" + var yes = true + for c in s do : + if not contains?(digits,c) : yes = false + yes + +public defn firrtl-gensym (s:Symbol,sym-hash:HashTable) -> Symbol : + defn get-name (s:Symbol) -> Symbol : + if key?(sym-hash,s) : + val num = sym-hash[s] + 1 + sym-hash[s] = num + symbol-join([s delin num]) + else : + sym-hash[s] = 0 + s + val s* = to-string(s) + val i* = for i in 0 to length(s*) - 1 find : + s*[i] == '_' and digits?(substring(s*,i + 1)) + match(i*) : + (i:False) : get-name(s) + (i:Int) : get-name(to-symbol(substring(s*,0,i))) + public defn get-sym-hash (m:InModule) -> HashTable : + get-sym-hash(m,list()) +public defn get-sym-hash (m:InModule,keywords:List) -> HashTable : val sym-hash = HashTable(symbol-hash) + for k in keywords do : + sym-hash[k] = 0 defn add-name (s:Symbol) -> False : - sym-hash[s] = 0 + val s* = to-string(s) + val i* = for i in 0 to length(s*) - 1 find : + s*[i] == '_' and digits?(substring(s*,i + 1)) + match(i*) : + (i:False) : + sym-hash[s] = 0 + (i:Int) : + val name = to-symbol(substring(s*,0,i)) + val digit = to-int(substring(s*,i + 1)) + if key?(sym-hash,name) : + val num = sym-hash[name] + sym-hash[name] = max(num,digit) + else : + sym-hash[name] = digit + defn to-port (p:Port) -> False : add-name(name(p)) defn to-stmt (s:Stmt) -> Stmt : match(s) : diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 4b99a4f8..e6d13196 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -295,12 +295,12 @@ public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars" defn get-new-string (n:Char) -> String : switch {n == _} : - ;'_' : "__" + '_' : "_" '~' : "$A" '!' : "$B" '@' : "$C" '#' : "$D" - ;'$' : "$E" + '$' : "$E" '%' : "$F" '^' : "$G" '*' : "$H" @@ -340,7 +340,7 @@ defn remove-special-chars (c:Circuit) : (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s)) (s) : map(rename-t,map(rename-s,s)) - Circuit(info(c),modules*, main(c)) where : + Circuit(info(c),modules*, rename(main(c))) where : val modules* = for m in modules(c) map : match(m) : @@ -1148,7 +1148,7 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable) -> Stmt : (s:ConnectToIndexed) : Begin $ if length(locs(s)) == 0 : list(EmptyStmt()) else : - val ref = WRef(firrtl-gensym(get-name(index(s)),sh,sub-delin),type(index(s)),NodeKind(),UNKNOWN-GENDER) + val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER) append( list(DefNode(info(s),name(ref),index(s))) to-list $ @@ -1162,7 +1162,7 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable) -> Stmt : (s:ConnectFromIndexed) : Begin $ if length(exps(s)) == 0 : list(EmptyStmt()) else : - val ref = WRef(firrtl-gensym(get-name(index(s)),sh,sub-delin),type(index(s)),NodeKind(),UNKNOWN-GENDER) + val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER) append( list(Connect(info(s),loc(s),head(exps(s))),DefNode(info(s),name(ref),index(s))) to-list $ @@ -1178,7 +1178,7 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable) -> Stmt : defn expand-connect-indexed (m: Module) -> Module : match(m) : (m:InModule) : - val sh = get-sym-hash(m) + val sh = get-sym-hash(m,v-keywords) InModule(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m),sh)) (m:ExModule) : m @@ -2176,8 +2176,8 @@ defn split-exp (c:Circuit) : ; if n typeof False : firrtl-gensym(`T,sh) ; else : firrtl-gensym(symbol-join([n as Symbol temp-delin]),sh) val n* = - if n typeof False : firrtl-gensym(`T,sh,temp-delin) - else : firrtl-gensym(n as Symbol,sh,temp-delin) + if n typeof False : firrtl-gensym(`T,sh) + else : firrtl-gensym(n as Symbol,sh) add(v,DefNode(info,n*,map(split-exp-e{_,n,info},e))) WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) ;else : e @@ -2204,7 +2204,7 @@ defn split-exp (c:Circuit) : match(m) : (m:InModule) : val v = Vector() - val sh = get-sym-hash(m) + val sh = get-sym-hash(m,v-keywords) ;val before = current-time-us() - start-time ;println-all(["Before split: " before]) split-exp-s(body(m),v,sh) diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir index e2dda086..f65d0aa9 100644 --- a/test/errors/gender/BulkWrong.fir +++ b/test/errors/gender/BulkWrong.fir @@ -13,4 +13,4 @@ circuit BTB : req <> x wire z : {x : UInt<1>, flip y : UInt<1> } - x.valid := r + x.valid := r.x diff --git a/test/errors/gender/bad_bulk_connect.fir b/test/errors/gender/bad_bulk_connect.fir new file mode 100644 index 00000000..f0891b9e --- /dev/null +++ b/test/errors/gender/bad_bulk_connect.fir @@ -0,0 +1,328 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; CHECK: Expression out.grant is used as a sink but can only be used as a source. + +circuit ClientTileLinkIOWrapper_49 : + module ClientTileLinkIOWrapper_49 : + input clock : Clock + input reset : UInt<1> + input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + + in.grant.bits.g_type := UInt<1>("h00") + in.grant.bits.is_builtin_type := UInt<1>("h00") + in.grant.bits.manager_xact_id := UInt<1>("h00") + in.grant.bits.client_xact_id := UInt<1>("h00") + in.grant.bits.data := UInt<1>("h00") + in.grant.bits.addr_beat := UInt<1>("h00") + in.grant.valid := UInt<1>("h00") + in.acquire.ready := UInt<1>("h00") + out.release.bits.voluntary := UInt<1>("h00") + out.release.bits.r_type := UInt<1>("h00") + out.release.bits.data := UInt<1>("h00") + out.release.bits.addr_beat := UInt<1>("h00") + out.release.bits.client_xact_id := UInt<1>("h00") + out.release.bits.addr_block := UInt<1>("h00") + out.release.valid := UInt<1>("h00") + out.probe.ready := UInt<1>("h00") + out.grant.ready := UInt<1>("h00") + out.acquire.bits.union := UInt<1>("h00") + out.acquire.bits.a_type := UInt<1>("h00") + out.acquire.bits.is_builtin_type := UInt<1>("h00") + out.acquire.bits.data := UInt<1>("h00") + out.acquire.bits.addr_beat := UInt<1>("h00") + out.acquire.bits.client_xact_id := UInt<1>("h00") + out.acquire.bits.addr_block := UInt<1>("h00") + out.acquire.valid := UInt<1>("h00") + + wire T_173394 : UInt<2>[2] + T_173394[0] := UInt<2>("h01") + T_173394[1] := UInt<2>("h02") + wire T_173397 : UInt<2>[2] + T_173397[0] := UInt<2>("h01") + T_173397[1] := UInt<2>("h02") + wire T_173399 : UInt<2>[1] + T_173399[0] := UInt<2>("h02") + wire T_173439 : UInt<2>[2] + T_173439[0] := UInt<2>("h01") + T_173439[1] := UInt<2>("h02") + wire T_173442 : UInt<2>[2] + T_173442[0] := UInt<2>("h01") + T_173442[1] := UInt<2>("h02") + wire T_173444 : UInt<2>[1] + T_173444[0] := UInt<2>("h02") + wire T_173483 : UInt<2>[2] + T_173483[0] := UInt<2>("h01") + T_173483[1] := UInt<2>("h02") + wire T_173486 : UInt<2>[2] + T_173486[0] := UInt<2>("h01") + T_173486[1] := UInt<2>("h02") + wire T_173488 : UInt<2>[1] + T_173488[0] := UInt<2>("h02") + wire T_173537 : UInt<2>[2] + T_173537[0] := UInt<2>("h01") + T_173537[1] := UInt<2>("h02") + wire T_173540 : UInt<2>[2] + T_173540[0] := UInt<2>("h01") + T_173540[1] := UInt<2>("h02") + wire T_173542 : UInt<2>[1] + T_173542[0] := UInt<2>("h02") + wire T_173588 : UInt<2>[2] + T_173588[0] := UInt<2>("h01") + T_173588[1] := UInt<2>("h02") + wire T_173591 : UInt<2>[2] + T_173591[0] := UInt<2>("h01") + T_173591[1] := UInt<2>("h02") + wire T_173593 : UInt<2>[1] + T_173593[0] := UInt<2>("h02") + wire T_173639 : UInt<2>[2] + T_173639[0] := UInt<2>("h01") + T_173639[1] := UInt<2>("h02") + wire T_173642 : UInt<2>[2] + T_173642[0] := UInt<2>("h01") + T_173642[1] := UInt<2>("h02") + wire T_173644 : UInt<2>[1] + T_173644[0] := UInt<2>("h02") + wire T_173692 : UInt<2>[2] + T_173692[0] := UInt<2>("h01") + T_173692[1] := UInt<2>("h02") + wire T_173695 : UInt<2>[2] + T_173695[0] := UInt<2>("h01") + T_173695[1] := UInt<2>("h02") + wire T_173697 : UInt<2>[1] + T_173697[0] := UInt<2>("h02") + wire T_173742 : UInt<2>[2] + T_173742[0] := UInt<2>("h01") + T_173742[1] := UInt<2>("h02") + wire T_173745 : UInt<2>[2] + T_173745[0] := UInt<2>("h01") + T_173745[1] := UInt<2>("h02") + wire T_173747 : UInt<2>[1] + T_173747[0] := UInt<2>("h02") + wire T_173795 : UInt<2>[2] + T_173795[0] := UInt<2>("h01") + T_173795[1] := UInt<2>("h02") + wire T_173798 : UInt<2>[2] + T_173798[0] := UInt<2>("h01") + T_173798[1] := UInt<2>("h02") + wire T_173800 : UInt<2>[1] + T_173800[0] := UInt<2>("h02") + wire T_173845 : UInt<2>[2] + T_173845[0] := UInt<2>("h01") + T_173845[1] := UInt<2>("h02") + wire T_173848 : UInt<2>[2] + T_173848[0] := UInt<2>("h01") + T_173848[1] := UInt<2>("h02") + wire T_173850 : UInt<2>[1] + T_173850[0] := UInt<2>("h02") + wire T_173895 : UInt<2>[2] + T_173895[0] := UInt<2>("h01") + T_173895[1] := UInt<2>("h02") + wire T_173898 : UInt<2>[2] + T_173898[0] := UInt<2>("h01") + T_173898[1] := UInt<2>("h02") + wire T_173900 : UInt<2>[1] + T_173900[0] := UInt<2>("h02") + wire T_173939 : UInt<2>[2] + T_173939[0] := UInt<2>("h01") + T_173939[1] := UInt<2>("h02") + wire T_173942 : UInt<2>[2] + T_173942[0] := UInt<2>("h01") + T_173942[1] := UInt<2>("h02") + wire T_173944 : UInt<2>[1] + T_173944[0] := UInt<2>("h02") + wire T_173993 : UInt<2>[2] + T_173993[0] := UInt<2>("h01") + T_173993[1] := UInt<2>("h02") + wire T_173996 : UInt<2>[2] + T_173996[0] := UInt<2>("h01") + T_173996[1] := UInt<2>("h02") + wire T_173998 : UInt<2>[1] + T_173998[0] := UInt<2>("h02") + wire T_174044 : UInt<2>[2] + T_174044[0] := UInt<2>("h01") + T_174044[1] := UInt<2>("h02") + wire T_174047 : UInt<2>[2] + T_174047[0] := UInt<2>("h01") + T_174047[1] := UInt<2>("h02") + wire T_174049 : UInt<2>[1] + T_174049[0] := UInt<2>("h02") + wire T_174095 : UInt<2>[2] + T_174095[0] := UInt<2>("h01") + T_174095[1] := UInt<2>("h02") + wire T_174098 : UInt<2>[2] + T_174098[0] := UInt<2>("h01") + T_174098[1] := UInt<2>("h02") + wire T_174100 : UInt<2>[1] + T_174100[0] := UInt<2>("h02") + wire T_174148 : UInt<2>[2] + T_174148[0] := UInt<2>("h01") + T_174148[1] := UInt<2>("h02") + wire T_174151 : UInt<2>[2] + T_174151[0] := UInt<2>("h01") + T_174151[1] := UInt<2>("h02") + wire T_174153 : UInt<2>[1] + T_174153[0] := UInt<2>("h02") + wire T_174198 : UInt<2>[2] + T_174198[0] := UInt<2>("h01") + T_174198[1] := UInt<2>("h02") + wire T_174201 : UInt<2>[2] + T_174201[0] := UInt<2>("h01") + T_174201[1] := UInt<2>("h02") + wire T_174203 : UInt<2>[1] + T_174203[0] := UInt<2>("h02") + wire T_174251 : UInt<2>[2] + T_174251[0] := UInt<2>("h01") + T_174251[1] := UInt<2>("h02") + wire T_174254 : UInt<2>[2] + T_174254[0] := UInt<2>("h01") + T_174254[1] := UInt<2>("h02") + wire T_174256 : UInt<2>[1] + T_174256[0] := UInt<2>("h02") + wire T_174301 : UInt<2>[2] + T_174301[0] := UInt<2>("h01") + T_174301[1] := UInt<2>("h02") + wire T_174304 : UInt<2>[2] + T_174304[0] := UInt<2>("h01") + T_174304[1] := UInt<2>("h02") + wire T_174306 : UInt<2>[1] + T_174306[0] := UInt<2>("h02") + wire T_174351 : UInt<2>[2] + T_174351[0] := UInt<2>("h01") + T_174351[1] := UInt<2>("h02") + wire T_174354 : UInt<2>[2] + T_174354[0] := UInt<2>("h01") + T_174354[1] := UInt<2>("h02") + wire T_174356 : UInt<2>[1] + T_174356[0] := UInt<2>("h02") + wire T_174395 : UInt<2>[2] + T_174395[0] := UInt<2>("h01") + T_174395[1] := UInt<2>("h02") + wire T_174398 : UInt<2>[2] + T_174398[0] := UInt<2>("h01") + T_174398[1] := UInt<2>("h02") + wire T_174400 : UInt<2>[1] + T_174400[0] := UInt<2>("h02") + wire T_174449 : UInt<2>[2] + T_174449[0] := UInt<2>("h01") + T_174449[1] := UInt<2>("h02") + wire T_174452 : UInt<2>[2] + T_174452[0] := UInt<2>("h01") + T_174452[1] := UInt<2>("h02") + wire T_174454 : UInt<2>[1] + T_174454[0] := UInt<2>("h02") + wire T_174500 : UInt<2>[2] + T_174500[0] := UInt<2>("h01") + T_174500[1] := UInt<2>("h02") + wire T_174503 : UInt<2>[2] + T_174503[0] := UInt<2>("h01") + T_174503[1] := UInt<2>("h02") + wire T_174505 : UInt<2>[1] + T_174505[0] := UInt<2>("h02") + wire T_174551 : UInt<2>[2] + T_174551[0] := UInt<2>("h01") + T_174551[1] := UInt<2>("h02") + wire T_174554 : UInt<2>[2] + T_174554[0] := UInt<2>("h01") + T_174554[1] := UInt<2>("h02") + wire T_174556 : UInt<2>[1] + T_174556[0] := UInt<2>("h02") + wire T_174604 : UInt<2>[2] + T_174604[0] := UInt<2>("h01") + T_174604[1] := UInt<2>("h02") + wire T_174607 : UInt<2>[2] + T_174607[0] := UInt<2>("h01") + T_174607[1] := UInt<2>("h02") + wire T_174609 : UInt<2>[1] + T_174609[0] := UInt<2>("h02") + wire T_174654 : UInt<2>[2] + T_174654[0] := UInt<2>("h01") + T_174654[1] := UInt<2>("h02") + wire T_174657 : UInt<2>[2] + T_174657[0] := UInt<2>("h01") + T_174657[1] := UInt<2>("h02") + wire T_174659 : UInt<2>[1] + T_174659[0] := UInt<2>("h02") + wire T_174707 : UInt<2>[2] + T_174707[0] := UInt<2>("h01") + T_174707[1] := UInt<2>("h02") + wire T_174710 : UInt<2>[2] + T_174710[0] := UInt<2>("h01") + T_174710[1] := UInt<2>("h02") + wire T_174712 : UInt<2>[1] + T_174712[0] := UInt<2>("h02") + wire T_174757 : UInt<2>[2] + T_174757[0] := UInt<2>("h01") + T_174757[1] := UInt<2>("h02") + wire T_174760 : UInt<2>[2] + T_174760[0] := UInt<2>("h01") + T_174760[1] := UInt<2>("h02") + wire T_174762 : UInt<2>[1] + T_174762[0] := UInt<2>("h02") + wire T_174807 : UInt<2>[2] + T_174807[0] := UInt<2>("h01") + T_174807[1] := UInt<2>("h02") + wire T_174810 : UInt<2>[2] + T_174810[0] := UInt<2>("h01") + T_174810[1] := UInt<2>("h02") + wire T_174812 : UInt<2>[1] + T_174812[0] := UInt<2>("h02") + wire T_174856 : UInt<2>[2] + T_174856[0] := UInt<2>("h01") + T_174856[1] := UInt<2>("h02") + wire T_174859 : UInt<2>[2] + T_174859[0] := UInt<2>("h01") + T_174859[1] := UInt<2>("h02") + wire T_174861 : UInt<2>[1] + T_174861[0] := UInt<2>("h02") + wire T_174902 : UInt<2>[2] + T_174902[0] := UInt<2>("h01") + T_174902[1] := UInt<2>("h02") + wire T_174905 : UInt<2>[2] + T_174905[0] := UInt<2>("h01") + T_174905[1] := UInt<2>("h02") + wire T_174907 : UInt<2>[1] + T_174907[0] := UInt<2>("h02") + wire T_174951 : UInt<2>[2] + T_174951[0] := UInt<2>("h01") + T_174951[1] := UInt<2>("h02") + wire T_174954 : UInt<2>[2] + T_174954[0] := UInt<2>("h01") + T_174954[1] := UInt<2>("h02") + wire T_174956 : UInt<2>[1] + T_174956[0] := UInt<2>("h02") + wire T_174997 : UInt<2>[2] + T_174997[0] := UInt<2>("h01") + T_174997[1] := UInt<2>("h02") + wire T_175000 : UInt<2>[2] + T_175000[0] := UInt<2>("h01") + T_175000[1] := UInt<2>("h02") + wire T_175002 : UInt<2>[1] + T_175002[0] := UInt<2>("h02") + wire T_175043 : UInt<2>[2] + T_175043[0] := UInt<2>("h01") + T_175043[1] := UInt<2>("h02") + wire T_175046 : UInt<2>[2] + T_175046[0] := UInt<2>("h01") + T_175046[1] := UInt<2>("h02") + wire T_175048 : UInt<2>[1] + T_175048[0] := UInt<2>("h02") + wire T_175096 : UInt<2>[2] + T_175096[0] := UInt<2>("h01") + T_175096[1] := UInt<2>("h02") + wire T_175099 : UInt<2>[2] + T_175099[0] := UInt<2>("h01") + T_175099[1] := UInt<2>("h02") + wire T_175101 : UInt<2>[1] + T_175101[0] := UInt<2>("h02") + wire T_175146 : UInt<2>[2] + T_175146[0] := UInt<2>("h01") + T_175146[1] := UInt<2>("h02") + wire T_175149 : UInt<2>[2] + T_175149[0] := UInt<2>("h01") + T_175149[1] := UInt<2>("h02") + wire T_175151 : UInt<2>[1] + T_175151[0] := UInt<2>("h02") + out.acquire <> in.acquire + out.grant <> in.grant + out.probe.ready := UInt<1>("h01") + out.release.valid := UInt<1>("h00") diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir index 00bb95a6..b721881e 100644 --- a/test/errors/type/Primop.fir +++ b/test/errors/type/Primop.fir @@ -1,8 +1,6 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Primop mux requires all operands to have the same type. ; CHECK: Primop add cannot operate on non-ground types. -; CHECK: Primop add cannot operate on non-ground types. -; CHECK: Primop bits requires all arguments to be UInt type. ; CHECK: Primop mux requires argument SInt("h00000001") to be a UInt type. circuit Top : diff --git a/test/features/EmptyStmt.fir b/test/features/EmptyStmt.fir new file mode 100644 index 00000000..c3bd894a --- /dev/null +++ b/test/features/EmptyStmt.fir @@ -0,0 +1,11 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: Done! +circuit Top : + module Top : + skip + when UInt(1) : + skip + else : + skip + skip + diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index e094abcc..70a52088 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -23,11 +23,11 @@ circuit top : ; CHECK: wire b{{[_$]+}}x : UInt<32> ; CHECK: wire b{{[_$]+}}y : UInt<32> ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x - ; CHECK: node i*0 = i - ; CHECK: when eqv(i*0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x - ; CHECK: node i*1 = i - ; CHECK: when eqv(i*1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y - ; CHECK: when eqv(i*1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: node i_1 = i + ; CHECK: when eqv(i_1, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: node i_2 = i + ; CHECK: when eqv(i_2, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: when eqv(i_2, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y j := b.x b.y := UInt(1) diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir new file mode 100644 index 00000000..3b120217 --- /dev/null +++ b/test/passes/split-exp/primop.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Split Expressions +circuit Top : + module Top : + output out : UInt<1> + output out2 : UInt<1> + + wire m : UInt<1>[3] + m[0] := UInt(0) + m[1] := UInt(0) + m[2] := UInt(0) + + wire x : UInt<1> + x := not(UInt(1)) + infer accessor a = m[x] + + out := a + + + -- cgit v1.2.3