From ff1cd28202fb423956a6803a889c3632487d8872 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Mon, 2 Aug 2021 16:35:00 -0400
Subject: Update spec to disallow 0-bit mux sel (#2305)

Change the FIRRTL spec to disallow a zero-width multiplexer select.
Clarify that the select line can be either one-bit or zero-bit, but will
infer to one-bit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 spec/spec.pdf | Bin 363498 -> 339523 bytes
 spec/spec.tex |   3 +--
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/spec/spec.pdf b/spec/spec.pdf
index d961a28d..b92c62e3 100644
Binary files a/spec/spec.pdf and b/spec/spec.pdf differ
diff --git a/spec/spec.tex b/spec/spec.tex
index d41d0562..a876aca9 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1307,9 +1307,8 @@ A multiplexer expression is legal only if the following holds.
 \item The type of the selection signal is an unsigned integer.
 \item The width of the selection signal is any of:
   \begin{enumerate}
-  \item Unspecified
-  \item Zero-bit\footnote{A zero-bit width selection signal will be treated as a one-bit, zero-valued selection signal.  \emph{This means that a multiplexer expression with a zero-bit selection signal will always take the false path and will likely be optimized away by a FIRRTL compiler.}}
   \item One-bit
+  \item Unspecified, but will infer to one-bit
   \end{enumerate}
 \item The types of the two input expressions are equivalent.
 \item The types of the two input expressions are passive (see section \ref{passive_types}).
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